Hansen Partnership Voyager Project

James Bottomley (James.Bottomley@HansenPartnership.com)

As part of its service to the Open Source Community, Hansen Partnership is sponsoring the Voyager Project to boot Linux on NCR Voyager Hardware.
 

Introduction

The voyager architecture was a multi-processing architecture (initially for the Intel 486 processor) which preceeded the Intel MP Specification.  Initially voyager began life as a dual CPU SMP model using the Micro Channel bus (called Level 3).  And eventually progressed to Level 5, which may have up to 32 processors and 4GB of memory per machine.  This project supports only Level 5 and Level 4 machines.

Voyager Machines (and their support status) are:
 

Class Level Size Support Description
51xx 5 enormous fridge Should boot
never tested
Usually MPP or Cluster data warehouse, up to 32 way SMP, primary and secondary MCA, always Q720 SCSI controller
35xx/36xx 5 large fridge Should boot
never tested
Usually data warehouse, up to 16 way SMP, primary and secondary MCA, may have either D700 or Q720 SCSI controller
345x/4100 5 standard server 
(waist high)
boots and tested (D700) depending on type can be up to 8 way SMP, primary MCA only, usually D700 SCSI, but may support Q720
3360/3430 4 smaller server boots and tested Up to 2 way SMP, primary MCA only, internal 53c710 SCSI controller.

Resources