Index: linux/2.2/Documentation/Configure.help diff -u linux/2.2/Documentation/Configure.help:1.1.1.13 linux/2.2/Documentation/Configure.help:1.1.1.13.4.1 --- linux/2.2/Documentation/Configure.help:1.1.1.13 Thu Feb 15 11:55:43 2001 +++ linux/2.2/Documentation/Configure.help Sat Feb 17 20:15:03 2001 @@ -1497,6 +1497,16 @@ Documentation/mca.txt (and especially the web page given there) before attempting to build an MCA bus kernel. +Support for the NCR Voyager Architecture +CONFIG_VOYAGER + Voyager is a MCA based 32 way capable SMP architecture proprietary + to NCR Corp. Machine classes 345x/35xx/51xx are voyager based. + + *** WARNING *** + + If you do not specifically know you have a Voyager based machine, + say N here otherwise the kernel you build will not be bootable. + SGI Visual Workstation support CONFIG_VISWS The SGI Visual Workstation series is an IA32-based workstation Index: linux/2.2/Documentation/voyager.txt diff -u /dev/null linux/2.2/Documentation/voyager.txt:1.1.10.1 --- /dev/null Sun Mar 4 11:35:05 2001 +++ linux/2.2/Documentation/voyager.txt Sat Feb 17 20:15:04 2001 @@ -0,0 +1,50 @@ +Running Linux on the Voyager Architecture +========================================= + +The voyager architecture was designed by NCR in the mid 80s to be a +fully SMP capable RAS computing architecture built around intel's 486 +chip set. The voyager came in three levels of architectural +sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype. +The linux patches support only the Level 5 voyager architecture (any +machine class 3435 and above). + +The Voyager Architecture +------------------------ + +Voyager machines consist of a Baseboard with a 386 diagnostic +processor, a Power Supply Interface (PSI) a Primary and possibly +Secondary Microchannel bus and between 4 and 20 voyager slots. The +voyager slots can be populated with memory and cpu cards (up to 4GB +memory and from 1 486 to 32 Pentium Pro processors). Internally, the +voyager has a dual arbitrated system bus and a configuration and test +bus (CAT). The voyager bus speed is 40MHz. Therefore (since all +voyager cards are dual ported for each system bus) the maximum +transfer rate is 320Mb/s but only if you have your slot configuration +tuned (only memory cards can communicate with both busses at once, CPU +cards utilise them one at a time). + +Voyager SMP +----------- + +Since voyager was the first intel based SMP system, it is slightly +more primitive than the Intel IO-APIC approach to SMP. Voyager allows +arbitrary interrupt routing (including processor affinity routing) of +all 16 PC type interrupts. However it does this by using a modified +5259 master/slave chip set instead of an APIC bus. Additionally, +voyager supports Cross Processor Interrupts (CPI) equivalent to the +APIC IPIs. There are two routed voyager interrupt lines provided to +each slot. + +Processor Cards +--------------- + +These come in single, dyadic and quad configurations (the quads are +problematic--see later). The maximum configuration is 8 quad cards +for 32 way SMP. + +Quad Processors +--------------- + +Because voyager only supplies two interrupt lines to each Processor +card, the Quad processors have to be configured (and Bootstrapped) in +as a pair of Master/Slave processors. Index: linux/2.2/arch/i386/config.in diff -u linux/2.2/arch/i386/config.in:1.1.1.7 linux/2.2/arch/i386/config.in:1.1.1.7.4.1 --- linux/2.2/arch/i386/config.in:1.1.1.7 Thu Feb 15 11:54:57 2001 +++ linux/2.2/arch/i386/config.in Sat Feb 17 20:15:04 2001 @@ -78,12 +78,15 @@ bool ' Backward-compatible /proc/pci' CONFIG_PCI_OLD_PROC fi bool 'MCA support' CONFIG_MCA +if [ "$CONFIG_MCA" = "y" ]; then + bool ' Support for the NCR Voyager Architecture' CONFIG_VOYAGER +fi bool 'SGI Visual Workstation support' CONFIG_VISWS if [ "$CONFIG_VISWS" = "y" ]; then define_bool CONFIG_X86_VISWS_APIC y define_bool CONFIG_X86_LOCAL_APIC y else - if [ "$CONFIG_SMP" = "y" ]; then + if [ "$CONFIG_SMP" = "y" -a "$CONFIG_VOYAGER" != "y" ]; then define_bool CONFIG_X86_IO_APIC y define_bool CONFIG_X86_LOCAL_APIC y fi Index: linux/2.2/arch/i386/boot/setup.S diff -u linux/2.2/arch/i386/boot/setup.S:1.1.1.4 linux/2.2/arch/i386/boot/setup.S:1.1.1.4.4.1 --- linux/2.2/arch/i386/boot/setup.S:1.1.1.4 Thu Feb 15 11:54:57 2001 +++ linux/2.2/arch/i386/boot/setup.S Sat Feb 17 20:15:04 2001 @@ -285,6 +285,7 @@ int 0x15 mov [2],ax + ! Set the keyboard repeat rate to the max mov ax,#0x0305 @@ -372,6 +373,26 @@ pop ds no_mca: +#ifdef CONFIG_VOYAGER + mov al,#0xff + mov [0x40], al ! flag on config found + mov al,#0xc0 + mov ah,#0xff + int 0x15 ! put voyager config info at es:di + jc no_voyager + mov si,#0x40 ! place voyager info in apm table + cld + mov cx,#7 +voyager_rep: + seg es + mov al,(di) + mov (si),al + inc di + inc si + dec cx + jnz voyager_rep +no_voyager: +#endif ! Check for PS/2 pointing device Index: linux/2.2/arch/i386/kernel/Makefile diff -u linux/2.2/arch/i386/kernel/Makefile:1.1.1.3 linux/2.2/arch/i386/kernel/Makefile:1.1.1.3.4.1 --- linux/2.2/arch/i386/kernel/Makefile:1.1.1.3 Thu Feb 15 11:54:59 2001 +++ linux/2.2/arch/i386/kernel/Makefile Sat Feb 17 20:15:04 2001 @@ -27,6 +27,10 @@ O_OBJS += mca.o endif +ifdef CONFIG_VOYAGER +O_OBJS += voyager.o voyager_cat.o +endif + ifeq ($(CONFIG_MTRR),y) OX_OBJS += mtrr.o else @@ -64,7 +68,11 @@ endif ifdef CONFIG_SMP +ifdef CONFIG_VOYAGER +O_OBJS += voyager_smp.o trampoline.o +else O_OBJS += smp.o trampoline.o +endif endif ifdef CONFIG_X86_IO_APIC Index: linux/2.2/arch/i386/kernel/head.S diff -u linux/2.2/arch/i386/kernel/head.S:1.1.1.1 linux/2.2/arch/i386/kernel/head.S:1.1.1.1.56.1 --- linux/2.2/arch/i386/kernel/head.S:1.1.1.1 Thu Mar 18 12:33:33 1999 +++ linux/2.2/arch/i386/kernel/head.S Sat Feb 17 20:15:04 2001 @@ -8,6 +8,7 @@ */ .text +#include #include #include #include @@ -49,7 +50,7 @@ movl %ax,%es movl %ax,%fs movl %ax,%gs -#ifdef __SMP__ +#if defined(__SMP__) && !defined(CONFIG_M486) orw %bx,%bx jz 1f /* @@ -210,7 +211,7 @@ orl $2,%eax # set MP 2: movl %eax,%cr0 call check_x87 -#ifdef __SMP__ +#if defined(__SMP__) && !defined(CONFIG_M486) movb ready,%al # First CPU if 0 orb %al,%al jz 4f # First CPU skip this stuff Index: linux/2.2/arch/i386/kernel/irq.c diff -u linux/2.2/arch/i386/kernel/irq.c:1.1.1.6 linux/2.2/arch/i386/kernel/irq.c:1.1.1.6.10.1 --- linux/2.2/arch/i386/kernel/irq.c:1.1.1.6 Tue Jun 13 19:25:12 2000 +++ linux/2.2/arch/i386/kernel/irq.c Sat Feb 17 20:15:04 2001 @@ -39,6 +39,9 @@ #include #include #include +#ifdef CONFIG_VOYAGER +#include +#endif #include "irq.h" @@ -292,7 +295,7 @@ */ BUILD_16_IRQS(0x0) -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_VOYAGER) /* * The IO-APIC gives us many more interrupt sources. Most of these * are unused but an SMP system is supposed to have enough memory ... @@ -313,7 +316,7 @@ #undef BI -#ifdef __SMP__ +#if defined(__SMP__) && !defined(CONFIG_VOYAGER) /* * The following vectors are part of the Linux architecture, there * is no hardware IRQ pin equivalent for them, they are triggered @@ -348,7 +351,7 @@ static void (*interrupt[NR_IRQS])(void) = { IRQLIST_16(0x0), -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_VOYAGER) IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), @@ -1104,6 +1107,11 @@ } #ifdef __SMP__ +#ifdef CONFIG_VOYAGER + + /* set up voyager SMP interrupts */ + voyager_smp_intr_init(); +#else /* IRQ0 must be given a fixed assignment and initialized @@ -1131,6 +1139,7 @@ /* IPI vector for APIC spurious interrupts */ set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); +#endif /* CONFIG_VOYAGER */ #endif request_region(0x20,0x20,"pic1"); request_region(0xa0,0x20,"pic2"); @@ -1142,6 +1151,10 @@ outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ outb_p(LATCH & 0xff , 0x40); /* LSB */ outb(LATCH >> 8 , 0x40); /* MSB */ + +#ifdef CONFIG_VOYAGER + voyager_setup_irqs(); +#endif #ifndef CONFIG_VISWS setup_x86_irq(2, &irq2); Index: linux/2.2/arch/i386/kernel/process.c diff -u linux/2.2/arch/i386/kernel/process.c:1.1.1.6 linux/2.2/arch/i386/kernel/process.c:1.1.1.6.4.1 --- linux/2.2/arch/i386/kernel/process.c:1.1.1.6 Thu Feb 15 11:55:00 2001 +++ linux/2.2/arch/i386/kernel/process.c Sat Feb 17 20:15:04 2001 @@ -32,6 +32,9 @@ #include #include #include +#ifdef CONFIG_VOYAGER +#include +#endif #include #include @@ -147,8 +150,9 @@ * controller to pulse the reset-line low. We try that for a while, * and if it doesn't work, we do some other stupid things. */ - +#ifndef CONFIG_VOYAGER static long no_idt[2] = {0, 0}; +#endif static int reboot_mode = 0; static int reboot_thru_bios = 0; @@ -176,7 +180,7 @@ } } - +#ifndef CONFIG_VOYAGER /* The following code and data reboots the machine by switching to real mode and jumping to the BIOS reset entry point, as if the CPU has really been reset. The previous version asked the keyboard @@ -237,6 +241,7 @@ { 0xea, 0x00, 0x00, 0xff, 0xff /* ljmp $0xffff,$0x0000 */ }; +#endif /* CONFIG VOYAGER */ static inline void kb_wait(void) { @@ -256,6 +261,21 @@ { unsigned long flags; +#ifdef CONFIG_VOYAGER + printk("Voyager Warm Restart\n"); + kb_wait(); + /* write magic values to the RTC to inform system that + * shutdown is beginning */ + outb(0x8f, 0x70); + outb(0x5 , 0x71); + + udelay(50); + outb(0xfe,0x64); /* pull reset low */ + for(;;) { + asm("cli"); + asm("hlt"); + } +#else cli(); /* Write zero to CMOS register number 0x0f, which the BIOS POST @@ -340,10 +360,14 @@ __asm__ __volatile__ ("ljmp $0x0008,%0" : : "i" ((void *) (0x1000 - sizeof (real_mode_switch) - 100))); +#endif /* CONFIG_VOYAGER */ } void machine_restart(char * __unused) { +#ifdef CONFIG_VOYAGER + machine_real_restart(NULL, 0); +#else #if CONFIG_SMP /* * turn off the IO-APIC, so we can do a clean reboot @@ -369,14 +393,33 @@ } machine_real_restart(jump_to_bios, sizeof(jump_to_bios)); +#endif /* CONFIG_VOYAGER */ } void machine_halt(void) { +#ifdef CONFIG_VOYAGER + /* treat a halt like a power off */ + machine_power_off(); +#endif } void machine_power_off(void) { +#ifdef CONFIG_VOYAGER + int port; + + /* enable the voyager Configuration Space */ + outb((inb(0x96) & 0xf0) | 0x8, 0x96); + /* the port for the power off flag is an offset from the + floating base */ + port = inb(0x99) * 0x100 + 0x21; + /* set the power off flag */ + outb(inb(port) | 0x1, port); + /* and wait for it to happen */ + for(;;) + ; +#endif if (acpi_power_off) acpi_power_off(); } Index: linux/2.2/arch/i386/kernel/setup.c diff -u linux/2.2/arch/i386/kernel/setup.c:1.1.1.9 linux/2.2/arch/i386/kernel/setup.c:1.1.1.9.4.1 --- linux/2.2/arch/i386/kernel/setup.c:1.1.1.9 Thu Feb 15 11:54:59 2001 +++ linux/2.2/arch/i386/kernel/setup.c Sat Feb 17 20:15:04 2001 @@ -74,6 +74,10 @@ #include #include +#ifdef CONFIG_VOYAGER +#include +#endif + /* * Machine setup.. */ @@ -91,6 +95,9 @@ unsigned int machine_id = 0; unsigned int machine_submodel_id = 0; unsigned int BIOS_revision = 0; +#ifdef CONFIG_VOYAGER +struct voyager_bios_info voyager_bios_info; +#endif unsigned int mca_pentium_flag = 0; /* @@ -123,7 +130,11 @@ #define SCREEN_INFO (*(struct screen_info *) (PARAM+0)) #define EXT_MEM_K (*(unsigned short *) (PARAM+2)) #define ALT_MEM_K (*(unsigned long *) (PARAM+0x1e0)) +#ifdef CONFIG_VOYAGER +#define VOYAGER_BIOS_INFO (*(struct voyager_bios_info *)(PARAM+0x40)) +#else #define APM_BIOS_INFO (*(struct apm_bios_info *) (PARAM+0x40)) +#endif #define DRIVE_INFO (*(struct drive_info_struct *) (PARAM+0x80)) #define SYS_DESC_TABLE (*(struct sys_desc_table_struct*)(PARAM+0xa0)) #define MOUNT_ROOT_RDONLY (*(unsigned short *) (PARAM+0x1F2)) @@ -289,7 +300,6 @@ ROOT_DEV = to_kdev_t(ORIG_ROOT_DEV); drive_info = DRIVE_INFO; screen_info = SCREEN_INFO; - apm_bios_info = APM_BIOS_INFO; if( SYS_DESC_TABLE.length != 0 ) { MCA_bus = SYS_DESC_TABLE.table[3] &0x2; machine_id = SYS_DESC_TABLE.table[0]; @@ -297,6 +307,33 @@ BIOS_revision = SYS_DESC_TABLE.table[2]; } aux_device_present = AUX_DEVICE_INFO; +#ifdef CONFIG_VOYAGER + voyager_bios_info = VOYAGER_BIOS_INFO; + if(voyager_bios_info.len != 0xff) { + int class = (voyager_bios_info.class_1 << 8) + | (voyager_bios_info.class_2 & 0xff); + int level; + + printk("Voyager System detected.\n\tClass %x, Revision %d.%d\n", + class, voyager_bios_info.major, + voyager_bios_info.minor); + if(class == VOYAGER_LEVEL4) + level = 4; + else if(class < VOYAGER_LEVEL5_AND_ABOVE) + level = 3; + else + level = 5; + printk("\tArchitecture Level %d\n", level); + if(level < 5) + printk("\n**WARNING**: Voyager HAL only supports Level5 Architectures at the moment\n\n"); + } + else { + printk("\n\n**WARNING**: No Voyager Subsystem Found\n"); + } + + memory_end = voyager_memory_detect(); +#else + apm_bios_info = APM_BIOS_INFO; memory_end = (1<<20) + (EXT_MEM_K<<10); #ifndef STANDARD_MEMORY_BIOS_CALL { @@ -306,6 +343,7 @@ memory_end = memory_alt_end; } #endif +#endif /* CONFIG_VOYAGER */ memory_end &= PAGE_MASK; #ifdef CONFIG_BLK_DEV_RAM Index: linux/2.2/arch/i386/kernel/time.c diff -u linux/2.2/arch/i386/kernel/time.c:1.1.1.6 linux/2.2/arch/i386/kernel/time.c:1.1.1.6.4.1 --- linux/2.2/arch/i386/kernel/time.c:1.1.1.6 Thu Feb 15 11:55:00 2001 +++ linux/2.2/arch/i386/kernel/time.c Sat Feb 17 20:15:04 2001 @@ -56,6 +56,10 @@ #include #include +#ifdef CONFIG_VOYAGER +#include +#endif + /* * for x86_do_profile() */ @@ -192,7 +196,11 @@ if( jiffies_t == jiffies_p ) { if( count > count_p ) { /* the nutcase */ - +#if defined(CONFIG_VOYAGER) && defined(__SMP__) + /* can't read the ISR, just assume 1 tick + overflow */ + count -= LATCH; +#else outb_p(0x0A, 0x20); /* assumption about timer being IRQ1 */ @@ -218,6 +226,7 @@ printk("do_slow_gettimeoffset(): hardware timer problem?\n"); #endif } +#endif /* CONFIG_VOYAGER && __SMP__ */ } } else jiffies_p = jiffies_t; @@ -384,9 +393,13 @@ if (!user_mode(regs)) x86_do_profile(regs->eip); #else +#ifdef CONFIG_VOYAGER + voyager_timer_interrupt(regs); +#else if (!smp_found_config) smp_local_timer_interrupt(regs); #endif +#endif /* * If we have an externally synchronized Linux clock, then update @@ -665,7 +678,8 @@ */ dodgy_tsc(); - + +#if defined(CONFIG_VOYAGER) && !defined(CONFIG_M486) if (boot_cpu_data.x86_capability & X86_FEATURE_TSC) { unsigned long tsc_quotient = calibrate_tsc(); if (tsc_quotient) { @@ -694,6 +708,7 @@ } } } +#endif #ifdef CONFIG_VISWS printk("Starting Cobalt Timer system clock\n"); Index: linux/2.2/arch/i386/kernel/traps.c diff -u linux/2.2/arch/i386/kernel/traps.c:1.1.1.4 linux/2.2/arch/i386/kernel/traps.c:1.1.1.4.4.1 --- linux/2.2/arch/i386/kernel/traps.c:1.1.1.4 Thu Feb 15 11:54:59 2001 +++ linux/2.2/arch/i386/kernel/traps.c Sat Feb 17 20:15:04 2001 @@ -42,6 +42,10 @@ #include #endif +#ifdef CONFIG_VOYAGER +#include +#endif + #include "irq.h" asmlinkage int system_call(void); @@ -706,6 +710,9 @@ set_trap_gate(17,&alignment_check); set_trap_gate(18,&machine_check); set_system_gate(SYSCALL_VECTOR,&system_call); +#ifdef CONFIG_VOYAGER + voyager_trap_init(); +#endif /* set up GDT task & ldt entries */ set_tss_desc(0, &init_task.tss); Index: linux/2.2/arch/i386/kernel/voyager.c diff -u /dev/null linux/2.2/arch/i386/kernel/voyager.c:1.1.10.1 --- /dev/null Sun Mar 4 11:35:10 2001 +++ linux/2.2/arch/i386/kernel/voyager.c Sat Feb 17 20:15:04 2001 @@ -0,0 +1,161 @@ +/* Copyright 1999 NCR Corporation - Dayton, Ohio, USA + * + * Author: James.Bottomley@ColumbiaSC.ncr.com + * + * linux/arch/i386/kernel/voyager.c + * + * This file contains all the voyager specific routines for getting + * initialisation of the architecture to function. For additional + * features see: + * + * voyager_cat.c - Voyager CAT bus interface + * voyager_smp.c - Voyager SMP hal (emulates linux smp.c) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq.h" + +void __init +voyager_trap_init(void) +{ + /* set up the additional trap gates needed */ + +} + +void +voyager_system_interrupt(int cpl, void *dev_id, struct pt_regs *regs) +{ + printk("Voyager: detected system interrupt\n"); +} + +void __init +voyager_setup_irqs(void) +{ +} + +/* Routine to read information from the extended CMOS area */ +__u8 +voyager_extended_cmos_read(__u16 addr) +{ + outb(addr & 0xff, 0x74); + outb((addr >> 8) & 0xff, 0x75); + return inb(0x76); +} + +/* internal definitions for the SUS Click Map of memory */ + +#define CLICK_ENTRIES 16 +#define CLICK_SIZE 4096 /* click to byte conversion for Length */ + +typedef struct ClickMap { + struct Entry { + __u32 Address; + __u32 Length; + } Entry[CLICK_ENTRIES]; +} ClickMap_t; + + +/* We rely on this being called before any other configuration functions. + * + * This is currently true in linux since memory sizing is done first. + * If this is no longer true move voyager_cat_init() to be called + * before any further configuration is done */ + +__u32 __init +voyager_memory_detect(void) +{ + int i; + __u32 size = 0; + __u8 cmos[4]; + ClickMap_t *map; + unsigned long map_addr; + unsigned long old; + + for(i = 0; i < sizeof(cmos); i++) + cmos[i] = voyager_extended_cmos_read(VOYAGER_MEMORY_CLICKMAP + i); + + map_addr = *(unsigned long *)cmos; + + /* steal page 0 for this */ + old = pg0[0]; + pg0[0] = ((map_addr & PAGE_MASK) | _PAGE_RW | _PAGE_PRESENT); + local_flush_tlb(); + /* now clear everything out but page 0 */ + map = (ClickMap_t *)(map_addr & (~PAGE_MASK)); + + /* The click map can contain up to CLICK_ENTRIES memory extents + * However, we can only cope with a PC like setup which has + * the basic memory and the extended memory, so behave like this + * is true */ + printk("\tBase Memory Size: %dk\n", + map->Entry[0].Length * CLICK_SIZE / 1024); + /* report size as being the end of extended memory (linux will fill + * in the holes in the base memory */ + size = map->Entry[1].Length * CLICK_SIZE + map->Entry[1].Address; + printk("\tExtended Memory Size: %dM\n", size / (1024 * 1024)); + if(map->Entry[2].Length != 0) + printk("**WARNING**: Voyager system has unused memory extents\n"); + /* replace the mapping */ + pg0[0] = old; + local_flush_tlb(); + voyager_cat_init(); + return size; +} + +void +voyager_dump() +{ + /* get here via a sysrq */ +#ifdef __SMP__ + voyager_smp_dump(); +#endif +} + +/* voyager specific handling code for timer interrupts. Used to hand + * off the timer tick to the SMP code, since the VIC doesn't have an + * internal timer (The QIC does, but that's another story). */ +void +voyager_timer_interrupt(struct pt_regs *regs) +{ + if((jiffies & 0x3ff) == 0) { + + /* There seems to be something flaky in either + * hardware or software that is resetting the timer 0 + * count to something much higher than it should be + * This seems to occur in the boot sequence, just + * before root is mounted. Therefore, every 10 + * seconds or so, we sanity check the timer zero count + * and kick it back to where it should be. + * + * FIXME: This is the most awful hack yet seen. I + * should work out exactly what is interfering with + * the timer count settings early in the boot sequence + * and swiftly introduce it to something sharp and + * pointy. */ + __u16 val; + + outb_p(0x00, 0x43); + val = inb_p(0x40); + val |= inb(0x40) << 8; + + if(val > LATCH) { + printk("\nVOYAGER: countdown timer value too high (%d), resetting\n\n", val); + outb(0x34,0x43); + outb_p(LATCH & 0xff , 0x40); /* LSB */ + outb(LATCH >> 8 , 0x40); /* MSB */ + } + } +#ifdef __SMP__ + smp_vic_timer_interrupt(regs); +#endif +} Index: linux/2.2/arch/i386/kernel/voyager_cat.c diff -u /dev/null linux/2.2/arch/i386/kernel/voyager_cat.c:1.1.10.1 --- /dev/null Sun Mar 4 11:35:10 2001 +++ linux/2.2/arch/i386/kernel/voyager_cat.c Sat Feb 17 20:15:04 2001 @@ -0,0 +1,457 @@ +/* -*- mode: c; c-basic-offset: 8 -*- */ + +/* Copyright 1999 NCR Corporation - Dayton, Ohio, USA + * + * Author: James.Bottomley@ColumbiaSC.ncr.com + * + * linux/arch/i386/kernel/voyager_cat.c + * + * This file contains all the logic for manipulating the CAT bus + * in a level 5 machine. + * + * The CAT bus is a serial configuration and test bus. Its primary + * uses are to probe the initial configuration of the system and to + * diagnose error conditions when a system interrupt occurs. The low + * level interface is fairly primitive, so most of this file consists + * of bit shift manipulations to send and receive packets on the + * serial bus */ + +#include +#include +#include +#include +#include +#include +#include + +/* the CAT command port */ +#define CAT_CMD (sspb + 0xe) +/* the CAT data port */ +#define CAT_DATA (sspb + 0xd) + +/* the internal cat functions */ +static void cat_pack(__u8 *msg, const __u16 start_bit, __u8 *data, + const __u16 num_bits); +static void cat_unpack(__u8 *msg, const __u16 start_bit, __u8 *data, + const __u16 num_bits); +static void cat_build_header(__u8 *header, const __u16 len, + const __u16 smallest_reg_bits, + const __u16 longest_reg_bits); +static int cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, + __u8 reg, __u8 op); +static int cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, + __u8 *value); +static int cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, + __u8 pad_bits); +static int cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, + __u8 value); +static int cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, + __u8 *value); +static int cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, + __u16 offset, __u16 len, void *buf); +static int cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp, + __u8 value); + + + +static int sspb = 0; + +voyager_module_t *voyager_cat_list; + +/* memory management won't be initialised when voyager_cat_init() is called + * so we need our own data structures + */ +static voyager_module_t voyager_module_storage[1]; +static voyager_asic_t voyager_asic_storage[1]; + + +/* This function is used to pack a data bit stream inside a message. + * It writes num_bits of the data buffer in msg starting at start_bit. + * Note: This function assumes that any unused bit in the data stream + * is set to zero so that the ors will work correctly */ +#define BITS_PER_BYTE 8 +static void +cat_pack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits) +{ + /* compute initial shift needed */ + const __u16 offset = start_bit % BITS_PER_BYTE; + const __u16 len = num_bits / BITS_PER_BYTE; + __u16 byte = len; + int i; + + /* clear out the bits */ + msg[byte] &= 0xff << (BITS_PER_BYTE - offset); + msg[byte++] |= data[0] >> offset; + if(len == 0) + return; + for(i = 0; i < len - (offset == 0) ? 0 : 1; i++) + msg[byte++] = (data[i] << (BITS_PER_BYTE - offset)) + | (data[i+1] >> offset); + if(offset != 0) { + msg[byte] &= 0xff >> offset; + msg[byte] |= data[i] << (BITS_PER_BYTE - offset); + } + return; +} +/* unpack the data again (same arguments as cat_pack()). data buffer + * must be zero populated + */ +static void +cat_unpack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits) +{ + /* compute initial shift needed */ + const __u16 offset = start_bit % BITS_PER_BYTE; + const __u16 len = num_bits / BITS_PER_BYTE; + __u16 byte = len; + int i; + + if(len == 0 && BITS_PER_BYTE - offset < num_bits) { + data[0] = msg[byte++] << offset; + data[0] &= 0xff << (BITS_PER_BYTE - num_bits); + return; + } + for(i = 0; i < len; i++) { + /* this annoying if has to be done just in case a read of + * msg one beyond the array causes a panic */ + if(offset != 0) { + data[i] = msg[byte++] << offset; + data[i] |= msg[byte] >> (BITS_PER_BYTE - offset); + } + else { + data[i] = msg[byte++]; + } + } + if(offset != 0) { + data[i] = msg[byte++] << offset; + data[i] &= 0xff << (BITS_PER_BYTE - num_bits); + } + return; +} + +static void +cat_build_header(__u8 *header, const __u16 len, const __u16 smallest_reg_bits, + const __u16 longest_reg_bits) +{ + int i; + __u16 start_bit = (smallest_reg_bits - 1) % BITS_PER_BYTE; + __u8 *last_byte = &header[len - 1]; + + for(i=0; i < len; i++) + header[i] = 0; + + for(i = start_bit; i > 0; i--) + *last_byte = ((*last_byte) << 1) + 1; + +} + +static int +cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 op) +{ + __u8 parity, inst; + __u8 iseq[VOYAGER_MAX_SCAN_PATH], hseq[VOYAGER_MAX_REG_SIZE]; + __u16 ibytes, hbytes, padbits; + + /* + * Parity is the parity of the register number + 1 (READ_REGISTER + * and WRITE_REGISTER always add '1' to the number of bits == 1) + */ + parity = (__u8)(1 + (reg & 0x01) + + ((__u8)(reg & 0x02) >> 1) + + ((__u8)(reg & 0x04) >> 2) + + ((__u8)(reg & 0x08) >> 3)) % 2; + + inst = ((parity << 7) | (reg << 2) | op); + + outb(VOYAGER_CAT_IRCYC, CAT_CMD); + outb(VOYAGER_CAT_HEADER, CAT_DATA); + outb(inst, CAT_DATA); + if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) + return 1; + ibytes = modp->inst_bits / BITS_PER_BYTE; + if((padbits = modp->inst_bits % BITS_PER_BYTE) != 0) { + padbits = BITS_PER_BYTE - padbits; + ibytes++; + } + hbytes = modp->largest_reg / BITS_PER_BYTE; + if(modp->largest_reg % BITS_PER_BYTE) + hbytes++; + cat_build_header(hseq, hbytes, modp->smallest_reg, modp->largest_reg); + cat_pack(iseq, modp->inst_bits, hseq, hbytes * BITS_PER_BYTE); + cat_pack(iseq, asicp->bit_location, &inst, asicp->ireg_length); + + if(cat_shiftout(iseq, ibytes, hbytes, padbits)) + return 1; + return 0; +} + +static int +cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 *value) +{ + if(asicp->asic_id == VOYAGER_CAT_ID) { + outb(VOYAGER_CAT_RUN, CAT_CMD); + outb(VOYAGER_CAT_DRCYC, CAT_CMD); + outb(VOYAGER_CAT_HEADER, CAT_DATA); + *value = inb(CAT_DATA); + outb(0xAA, CAT_DATA); + if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) + return 1; + return 0; + } + else { + __u16 sbits = modp->num_asics -1 + asicp->ireg_length; + __u16 sbytes = sbits / BITS_PER_BYTE; + __u16 tbytes; + __u8 string[VOYAGER_MAX_SCAN_PATH], trailer[VOYAGER_MAX_REG_SIZE]; + __u8 padbits; + int i; + + outb(VOYAGER_CAT_DRCYC, CAT_CMD); + + if((padbits = sbits % BITS_PER_BYTE) != 0) { + padbits = BITS_PER_BYTE - padbits; + sbytes++; + } + tbytes = asicp->ireg_length / BITS_PER_BYTE; + if(asicp->ireg_length % BITS_PER_BYTE) + tbytes++; + cat_build_header(trailer, tbytes, 1, asicp->ireg_length); + + for(i = tbytes -1; i>=0; i--) { + outb(trailer[i], CAT_DATA); + string[sbytes + i] = inb(CAT_DATA); + } + + for(i = sbytes - 1; i>=0; i--) { + outb(0xaa, CAT_DATA); + string[i] = inb(CAT_DATA); + } + *value = 0; + cat_unpack(string, padbits + (tbytes * BITS_PER_BYTE) + asicp->asic_location, value, asicp->ireg_length); + + /* sanity check the rest of the return */ + for(i=0; i < tbytes; i++) { + __u8 input = 0; + cat_unpack(string, padbits + (i * BITS_PER_BYTE), &input, BITS_PER_BYTE); + if(trailer[i] != input) + return 1; + } + return 0; + } +} + +static int +cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, __u8 pad_bits) +{ + int i; + + for(i = data_bytes + header_bytes - 1; i >= header_bytes; i--) + outb(data[i], CAT_DATA); + + for(i = header_bytes - 1; i >= 0; i--) { + __u8 header = 0; + __u8 input; + + outb(data[i], CAT_DATA); + input = inb(CAT_DATA); + cat_unpack(data, ((data_bytes + 1) * BITS_PER_BYTE) - pad_bits, + &header, BITS_PER_BYTE); + if(input != header) + return 1; + } + return 0; +} + +static int +cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 value) +{ + outb(VOYAGER_CAT_DRCYC, CAT_CMD); + if(asicp->asic_id == VOYAGER_CAT_ID) { + outb(VOYAGER_CAT_HEADER, CAT_DATA); + outb(value, CAT_DATA); + if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) + return 1; + outb(VOYAGER_CAT_END, CAT_CMD); + outb(VOYAGER_CAT_RUN, CAT_CMD); + + return 0; + } + else { + __u16 hbytes = asicp->ireg_length / BITS_PER_BYTE; + __u16 dbytes = modp->num_asics - 1 + hbytes; + __u8 padbits, dseq[VOYAGER_MAX_SCAN_PATH], + hseq[VOYAGER_MAX_REG_SIZE]; + int i; + + if((padbits = modp->num_asics - 1 + + (asicp->ireg_length % BITS_PER_BYTE)) != 0) { + padbits = BITS_PER_BYTE - padbits; + dbytes++; + } + if(asicp->ireg_length % BITS_PER_BYTE) + hbytes++; + + cat_build_header(hseq, hbytes, 1, asicp->ireg_length); + + for(i = 0; i < dbytes + hbytes; i++) + dseq[i] = 0xff; + cat_pack(dseq, modp->num_asics - 1 + asicp->ireg_length, + hseq, hbytes * BITS_PER_BYTE); + cat_pack(dseq, asicp->asic_location, &value, + asicp->ireg_length); + return cat_shiftout(dseq, dbytes, hbytes, padbits); + } +} + +static int +cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, + __u8 value) +{ + if(cat_sendinst(modp, asicp, reg, VOYAGER_WRITE_CONFIG)) + return 1; + return cat_senddata(modp, asicp, value); +} + +static int +cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, + __u8 *value) +{ + if(cat_sendinst(modp, asicp, reg, VOYAGER_READ_CONFIG)) + return 1; + return cat_getdata(modp, asicp, value); +} + + + +static int +cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset, + __u16 len, void *buf) +{ + int i; + + if(len > 1) { + /* set auto increment */ + __u8 val; + + if(cat_read(modp, asicp, VOYAGER_AUTO_INC_REG, &val)) { + printk(KERN_WARNING "cat_subread: read of VOYAGER_AUTO_INC_REG\n"); + return 1; + } + val |= VOYAGER_AUTO_INC; + if(cat_write(modp, asicp, VOYAGER_AUTO_INC_REG, val)) { + printk(KERN_WARNING "cat_subread: write to VOYAGER_AUTO_INC_REG\n"); + return 1; + } + } + if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_READ_CONFIG)) + return 1; + for(i = 0; i < len; i++) { + if(cat_getdata(modp, asicp, &((__u8 *)buf)[i])) { + printk(KERN_WARNING "cat_subread: cat_getdata element %d failed\n", i); + return 1; + } + } + return 0; +} + + +/* buffer for storing EPROM data read in during initialisation */ +static __initdata __u8 eprom_buf[1]; + +void +voyager_cat_init(void) +{ + voyager_module_t **modpp = &voyager_cat_list; + voyager_asic_t **asicpp; + int i, cat_count = 0, asic_count = 0; + voyager_eprom_hdr_t *eprom_hdr = (voyager_eprom_hdr_t *)&eprom_buf[0]; + /* set up the SuperSet Port Block which tells us where the + * CAT communication port is */ + sspb = inb(VOYAGER_SSPB_RELOCATION_PORT) * 0x100; + VDEBUG(("VOYAGER DEBUG: sspb = 0x%x\n", sspb)); + + for(i = VOYAGER_MIN_MODULE; + i <= VOYAGER_MAX_MODULE; i++) { + __u8 input; + int asic; + __u16 eprom_size; + __u16 sp_offset; + + outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT); + outb(i, VOYAGER_CAT_CONFIG_PORT); + + /* check the presence of the module */ + outb(VOYAGER_CAT_RUN, CAT_CMD); + outb(VOYAGER_CAT_IRCYC, CAT_CMD); + outb(VOYAGER_CAT_HEADER, CAT_DATA); + /* stream series of alternating 1's and 0's to stimulate + * response */ + outb(0xAA, CAT_DATA); + input = inb(CAT_DATA); + outb(VOYAGER_CAT_END, CAT_CMD); + if(input != VOYAGER_CAT_HEADER) { + continue; + } + VDEBUG(("VOYAGER DEBUG: found module id %d\n", i)); + if(cat_count > VOYAGER_MAX_MODULES) { + printk("**WARNING**: Voyager out of module allocation space (max=%d)\n", cat_count); + break; + } + *modpp = &voyager_module_storage[cat_count++]; + /* need temporary asic for cat_subread. It will be + * filled in correctly later */ + (*modpp)->asic = &voyager_asic_storage[asic_count]; + if(cat_subread(*modpp, (*modpp)->asic, + VOYAGER_EPROM_SIZE_OFFSET, sizeof(eprom_size), + &eprom_size)) { + printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x, asic (0x%x:0x%x)\n", i, (*modpp)->asic->asic_type, + (*modpp)->asic->asic_id); + continue; + } + if(eprom_size > sizeof(eprom_buf)) { + printk("**WARNING**: Voyager insufficient size to read EPROM data. Need %d\n", eprom_size); + continue; + } + if(cat_subread(*modpp, (*modpp)->asic, 0, + eprom_size, eprom_buf)) + continue; + (*modpp)->ee_size = eprom_hdr->ee_size; + (*modpp)->num_asics = eprom_hdr->num_asics; + asicpp = &((*modpp)->asic); + sp_offset = eprom_hdr->scan_path_offset; + for(asic=0; asic < (*modpp)->num_asics; asic++) { + int j; + voyager_asic_t *asicp = *asicpp + = &voyager_asic_storage[asic_count++]; + voyager_sp_table_t *sp_table; + voyager_at_t *asic_table; + voyager_jtt_t *jtag_table; + + asicpp = &(asicp->next); + asicp->asic_location = asic; + sp_table = (voyager_sp_table_t *)(eprom_buf + sp_offset); + asicp->asic_id = sp_table->asic_id; + asic_table = (voyager_at_t *)(eprom_buf + sp_table->asic_data_offset); + for(j=0; j<4; j++) + asicp->jtag_id[j] = asic_table->jtag_id[j]; + jtag_table = (voyager_jtt_t *)(eprom_buf + asic_table->jtag_offset); + asicp->ireg_length = jtag_table->ireg_len; + asicp->bit_location = (*modpp)->inst_bits; + (*modpp)->inst_bits += asicp->ireg_length; + if(asicp->ireg_length > (*modpp)->largest_reg) + (*modpp)->largest_reg = asicp->ireg_length; + if (asicp->ireg_length < (*modpp)->smallest_reg || + (*modpp)->smallest_reg == 0) + (*modpp)->smallest_reg = asicp->ireg_length; + sp_offset += sizeof(voyager_sp_table_t); + } + *asicpp = NULL; + modpp = &((*modpp)->next); + } + *modpp = NULL; +} + +int +voyager_cat_readb(__u8 module, __u8 asic, int reg) +{ + return 0; +} Index: linux/2.2/arch/i386/kernel/voyager_smp.c diff -u /dev/null linux/2.2/arch/i386/kernel/voyager_smp.c:1.1.10.1 --- /dev/null Sun Mar 4 11:35:10 2001 +++ linux/2.2/arch/i386/kernel/voyager_smp.c Sat Feb 17 20:15:04 2001 @@ -0,0 +1,1306 @@ +/* -*- mode: c; c-basic-offset: 8 -*- */ + +/* Copyright 1999 NCR Corporation - Dayton, Ohio, USA + * + * Author: James.Bottomley@ColumbiaSC.ncr.com + * + * linux/arch/i386/kernel/voyager_smp.c + * + * This file provides all the same external entries as smp.c but uses + * the voyager hal to provide the functionality + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq.h" + +/* The global kernel spinlock */ +spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED; + +/* Set when the idlers are all forked - Set in main.c but not actually + * used by any other parts of the kernel */ +int smp_threads_ready = 0; + +/* per CPU data structure (for /proc/cpuinfo et al) */ +struct cpuinfo_x86 cpu_data[NR_CPUS]; + +/* physical ID of the CPU used to boot the system */ +unsigned char boot_cpu_id; + +/* which logical number maps to which CPU */ +volatile int __cpu_logical_map[NR_CPUS]; + +/* which physical CPU maps to which logical number */ +volatile int cpu_number_map[NR_CPUS]; + +/* Total count of live CPUs, used in process.c to display + * the CPU information and in irq.c for the per CPU irq + * activity count. Finally exported by i386_ksyms.c */ +int smp_num_cpus = 1; + +/* Number of CPIs delivered */ +volatile unsigned long ipi_count; + +/* Have we found an SMP box - used by time.c to do the profiling + interrupt for timeslicing; do not set to 1 until the per CPU timer + interrupt is active */ +int smp_found_config = 0; + +/* Used for the invalidate map that's also checked in the spinlock */ +volatile unsigned long smp_invalidate_needed; + +/* Bitmask of currently online CPUs - used by setup.c for /proc/cpuinfo */ +unsigned long cpu_online_map = 0; + +/* Bitmask of CPUs present in the system - exported by i386_syms.c */ +unsigned long cpu_present_map = 0; + +/* estimate of time used to flush the SMP-local cache - used in + * processor affinity calculations */ +cycles_t cacheflush_time = 0; + +/* The internal functions */ +static void send_CPI(__u32 cpuset, __u8 cpi); +static void send_one_CPI(__u8 cpu, __u8 cpi); +static void ack_CPI(__u8 cpu); +static void send_CPI_allbutself(__u8 cpi); +static void enable_vic_irq(unsigned int irq); +static void disable_vic_irq(unsigned int irq); +static void enable_local_vic_irq(unsigned int irq); +static void disable_local_vic_irq(unsigned int irq); +static void do_vic_irq(unsigned int irq, struct pt_regs *regs); +static void ack_vic_irq(unsigned int irq); +static void vic_enable_cpi(void); + +int hard_smp_processor_id(void); + + +/* local variables */ + +/* The VIC IRQ descriptors -- these look almost identical to the + * 8259 IRQs except that masks and things must be kept per processor + */ +static struct hw_interrupt_type vic_irq_type = { + "VIC-level", + enable_vic_irq, /* startup */ + disable_vic_irq, /* shutdown */ + do_vic_irq, /* do */ + enable_vic_irq, /* enable */ + disable_vic_irq /* disable */ +}; + +/* used to count up as CPUs are brought on line (starts at 0) */ +static int cpucount = 0; + +/* steal a page from the bottom of memory for the trampoline and + * squirrel its address away here. This will be in kernel virtual + * space */ +static __u32 trampoline_base; + +/* The per cpu profile stuff - used in smp_local_timer_interrupt */ +static unsigned int prof_multiplier[NR_CPUS]; +static unsigned int prof_counter[NR_CPUS]; + +/* the map used to check if a CPU has booted */ +__u32 cpu_booted_map; + +/* the synchronize flag used to hold all secondary CPUs spinning in + * a tight loop until the boot sequence is ready for them */ +static atomic_t smp_commenced = ATOMIC_INIT(0); + +/* The per processor IRQ masks (these are usually kept in sync) */ +static __u16 vic_irq_mask[NR_CPUS]; + +/* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */ +static __u16 vic_irq_enable_mask[NR_CPUS] = { 0 }; + +/* Lock for enable/disable of VIC interrupts */ +static spinlock_t vic_irq_lock = SPIN_LOCK_UNLOCKED; + +/* The boot processor is correctly set up in PC mode when it + * comes up, but the secondaries need their master/slave 8259 + * pairs initializing correctly */ + +/* Interrupt counters (per cpu) and total - used to try to + * even up the interrupt handling routines */ +static long vic_intr_total = 0; +static long vic_intr_count[NR_CPUS] = { 0 }; +static unsigned long vic_tick[NR_CPUS] = { 0 }; + +/* Since we can only use CPI0, we fake all the other CPIs */ +static unsigned long vic_cpi_mailbox[NR_CPUS]; + +/* debugging routine to read the isr of the cpu's pic */ +static inline __u16 +vic_read_isr(void) +{ + __u16 isr; + + outb(0x0b, 0xa0); + isr = inb(0xa0) << 8; + outb(0x0b, 0x20); + isr |= inb(0x20); + + return isr; +} + +static __init void +vic_setup_pic(void) +{ + outb(1, VIC_REDIRECT_REGISTER_1); + /* clear the claim registers for dynamic routing */ + outb(0, VIC_CLAIM_REGISTER_0); + outb(0, VIC_CLAIM_REGISTER_1); + + outb(0, VIC_PRIORITY_REGISTER); + /* Set the Primary and Secondary Microchannel vector + * bases to be the same as the ordinary interrupts + * + * FIXME: This would be more efficient using separate + * vectors. */ + outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE); + outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE); + /* Now initiallise the master PIC belonging to this CPU by + * sending the four ICWs */ + + /* ICW1: level triggered, ICW4 needed */ + outb(0x19, 0x20); + + /* ICW2: vector base */ + outb(FIRST_EXTERNAL_VECTOR, 0x21); + + /* ICW3: slave at line 2 */ + outb(0x04, 0x21); + + /* ICW4: 8086 mode */ + outb(0x01, 0x21); + + /* now the same for the slave PIC */ + + /* ICW1: level trigger, ICW4 needed */ + outb(0x19, 0xA0); + + /* ICW2: slave vector base */ + outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1); + + /* ICW3: slave ID */ + outb(0x02, 0xA1); + + /* ICW4: 8086 mode */ + outb(0x01, 0xA1); +} + + + +/* Set up all the basic stuff: read the SMP config and make all the + * SMP information reflect only the boot cpu. All others will be + * brought on-line later. */ +void __init +init_smp_config(void) +{ + int i; + + boot_cpu_id = hard_smp_processor_id(); + + VDEBUG(("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id)); + /* set up everything for just this CPU, we can alter + * this as we start the other CPUs later */ + smp_num_cpus = 1; + current->processor = boot_cpu_id; + for(i=0; ipte_quick = 0; + c->pgd_quick = 0; + c->pgtable_cache_sz = 0; + identify_cpu(c); +} + +/* set up the trampoline and return the physical address of the code */ +static __u32 __init +setup_trampoline(void) +{ + /* these two are global symbols in trampoline.S */ + extern __u8 trampoline_end[]; + extern __u8 trampoline_data[]; + + memcpy((__u8 *)trampoline_base, trampoline_data, + trampoline_end - trampoline_data); + return virt_to_phys((__u8 *)trampoline_base); +} + +/* Routine initially called when a non-boot CPU is brought online */ +int __init +start_secondary(void *unused) +{ + __u8 cpuid = hard_smp_processor_id(); + /* external functions not defined in the headers */ + extern void calibrate_delay(void); + extern int cpu_idle(void * unused); + + /* OK, we're in the routine */ + ack_CPI(VIC_CPU_BOOT_CPI); + + /* enable interrupts */ + __sti(); + + /* get our bogomips */ + calibrate_delay(); + + /* save our processor parameters */ + smp_store_cpu_info(cpuid); + + /* setup the 8259 master slave pair belonging to this CPU --- + * we won't actually receive any until the boot CPU + * relinquishes it's static routing mask */ + vic_setup_pic(); + + /* lower the mask to receive CPIs */ + vic_enable_cpi(); + + VDEBUG(("VOYAGER SMP; CPU%d, stack at about %p\n", cpuid, &cpuid)); + + /* Unblock the master CPU _only_ when the scheduler state of + * all secondary CPUs will be up-to-date, so after the SMP + * initialization the master will be just allowed to call the + * scheduler code. */ + init_idle(); + + /* signal that we're done */ + cpu_booted_map = 1; + + while(!atomic_read(&smp_commenced)) + /* nothing */; + + return cpu_idle(NULL); +} + +static int __init +fork_by_hand(void) +{ + struct pt_regs regs; + /* don't care about the eip and regs settings since we'll + * never reschedule the forked task. */ + return do_fork(CLONE_VM|CLONE_PID, 0, ®s); +} + + +/* Routine to kick start the given CPU and wait for it to report ready + * (or timeout in startup). When this routine returns, the requested + * CPU is either fully running and configured or known to be dead. + * + * We call this routine sequentially 1 CPU at a time, so no need for + * locking */ + +void __init +do_boot_cpu(__u8 cpu) +{ + struct task_struct *idle; + int timeout; + unsigned long flags; + /* For the 486, we can't use the 4Mb page table trick, so + * must map a region of memory */ +#ifdef CONFIG_M486 + int i; + unsigned long *page_table_copies = (unsigned long *) + __get_free_page(GFP_KERNEL); +#endif + pgd_t orig_swapper_pg_dir0; + + /* This is an area in head.S which was used to set up the + * initial kernel stack. We need to alter this to give the + * booting CPU a new stack (taken from its idle process) */ + extern struct { + __u8 *esp; + unsigned short ss; + } stack_start; + /* This is the format of the CPI IDT gate (in real mode) which + * we're hijacking to boot the CPU */ + union IDTFormat { + struct seg { + __u16 Offset; + __u16 Segment; + } idt; + __u32 val; + } hijack_source; + + __u32 *hijack_vector; + __u32 start_phys_address = setup_trampoline(); + + /* enable our own CPIs */ + vic_enable_cpi(); + + /* There's a clever trick to this: The linux trampoline is + * compiled to begin at absolute location zero, so make the + * address zero but have the data segment selector compensate + * for the actual address */ + hijack_source.idt.Offset = start_phys_address & 0x000F; + hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF; + + cpucount++; + if(fork_by_hand() < 0) + panic("failed fork for CPU%d", cpu); + + idle = task[cpucount]; + if (!idle) + panic("No idle process for CPU %d", cpu); + idle->processor = cpu; + __cpu_logical_map[cpucount] = cpu; + cpu_number_map[cpu] = cpucount; + idle->has_cpu = 1; /* we schedule the first task manually */ + idle->tss.eip = (unsigned long) start_secondary; + stack_start.esp = (1024 + PAGE_SIZE + (__u8 *)idle); + /* Note: Don't modify initial ss override */ + VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x]\n", cpu, + (unsigned long)hijack_source.val, hijack_source.idt.Segment, + hijack_source.idt.Offset)); + /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently + * (so that the booting CPU can find start_32 */ + orig_swapper_pg_dir0 = swapper_pg_dir[0]; +#ifdef CONFIG_M486 + if(page_table_copies == NULL) + panic("No free memory for 486 page tables\n"); + for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++) + page_table_copies[i] = (i * PAGE_SIZE) + | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; + + ((unsigned long *)swapper_pg_dir)[0] = + ((virt_to_phys(page_table_copies)) & PAGE_MASK) + | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; +#else + ((unsigned long *)swapper_pg_dir)[0] = 0x102007; +#endif + + hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4); + *hijack_vector = hijack_source.val; + /* VIC errata, may also receive interrupt at this address */ + hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4); + *hijack_vector = hijack_source.val; + + /* All non-boot CPUs start with interrupts fully masked. Need + * to lower the mask of the CPI we're about to send. We do + * this in the VIC by masquerading as the processor we're + * about to boot and lowering its interrupt mask */ + __save_flags(flags); + __cli(); + outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID); + /* here we're altering registers belonging to `cpu' */ + outb(VIC_BOOT_INTERRUPT_MASK, 0x21); + /* now go back to our original identity */ + outb(boot_cpu_id, VIC_PROCESSOR_ID); + cpu_booted_map = 0; + /* and boot the CPU */ + + send_one_CPI(cpu, VIC_CPU_BOOT_CPI); + __restore_flags(flags); + + /* now wait for it to become ready (or timeout) */ + for(timeout = 0; timeout < 50000; timeout++) { + if(cpu_booted_map) + break; + udelay(100); + } + /* reset the page table */ + swapper_pg_dir[0] = orig_swapper_pg_dir0; + local_flush_tlb(); +#ifdef CONFIG_M486 + free_page((unsigned long)page_table_copies); +#endif + + if(cpu_booted_map) { + cpu_number_map[cpu] = cpucount; + __cpu_logical_map[cpucount] = cpu; + + printk("CPU%d: ", cpu); + print_cpu_info(&cpu_data[cpu]); + cpu_online_map |= (1<tss; + + /* + * Load up the LDT and the task register. + */ + asm volatile("lldt %%ax": :"a" (p->ldt)); + asm volatile("ltr %%ax": :"a" (p->tr)); + stts(); + + /* + * We don't actually need to load the full TSS, + * basically just the stack pointer and the eip. + */ + + asm volatile( + "movl %0,%%esp\n\t" + "jmp *%1" + : + :"r" (p->esp),"r" (p->eip)); +} + +/* Used by do_none in irq.c to acknowledge receipt of an interrupt + * for which we have no handler */ +void +ack_APIC_irq(void) +{ +} + +/* handle a Voyager SYS_INT -- If we don't, the base board will + * panic the system. + * + * System interrupts occur because some problem was detected on the + * various busses. To find out what you have to probe all the + * hardware via the CAT bus. FIXME: At the moment we do nothing. */ +asmlinkage void +smp_vic_sys_interrupt(void) +{ + ack_CPI(VIC_SYS_INT); + printk("Voyager SYSTEM INTERRUPT\n"); +} + +/* Handle a voyager CMN_INT; These interrupts occur either because of + * a system status change or because a single bit memory error + * occurred. FIXME: At the moment, ignore all this. */ +asmlinkage void +smp_vic_cmn_interrupt(void) +{ + ack_CPI(VIC_CMN_INT); + printk("Voyager COMMON INTERRUPT\n"); +} + +/* + * Reschedule call back. Nothing to do, all the work is done + * automatically when we return from the interrupt. */ +asmlinkage void +smp_reschedule_interrupt(void) +{ + /* do nothing */ +} +/* + * Invalidate call-back + */ +asmlinkage void +smp_invalidate_interrupt(void) +{ + if (test_and_clear_bit(smp_processor_id(), &smp_invalidate_needed)) + local_flush_tlb(); + /* This will flood messages. Don't uncomment unless you see + * Problems with cross cpu invalidation + VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n", + smp_processor_id())); + */ +} + +/* enable the requested IRQs */ +asmlinkage void +smp_enable_irq_interrupt(void) +{ + __u8 irq; + __u8 cpu = smp_processor_id(); + + VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu, + vic_irq_enable_mask[cpu])); + + spin_lock(&vic_irq_lock); + for(irq = 0; irq < 16; irq++) { + if(vic_irq_enable_mask[cpu] & (1< The function to run. This must be fast and non-blocking. + An arbitrary pointer to pass to the function. + If true, keep retrying until ready. + If true, wait until function has completed on other CPUs. + [RETURNS] 0 on success, else a negative status code. Does not return until + remote CPUs are nearly ready to execute <> or are or have executed. +*/ +int +smp_call_function (void (*func) (void *info), void *info, int retry, + int wait) +{ + return 0; +} + +/* Sorry about the name. In an APIC based system, the APICs + * themselves are programmed to send a timer interrupt. This is used + * by linux to reschedule the processor. Voyager doesn't have this, + * so we use the system clock to interrupt one processor, which in + * turn, broadcasts a timer CPI to all the others --- we receive that + * CPI here. We don't use this actually for counting so losing + * ticks doesn't matter */ +asmlinkage void +smp_apic_timer_interrupt(struct pt_regs * regs) +{ + smp_local_timer_interrupt(regs); +} + +asmlinkage void +smp_vic_cpi_interrupt(struct pt_regs *regs) +{ + __u8 cpu = smp_processor_id(); + + if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu])) + smp_local_timer_interrupt(regs); + if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu])) + smp_invalidate_interrupt(); + if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu])) + smp_invalidate_interrupt(); + if(test_and_clear_bit(VIC_STOP_CPU_CPI, &vic_cpi_mailbox[cpu])) + smp_stop_cpu_interrupt(); + if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu])) + smp_enable_irq_interrupt(); + ack_CPI(VIC_CPI_LEVEL0); +} + + + + + +/* flush the TLB of every active CPU in the system */ +void +smp_flush_tlb(void) +{ + __u8 cpu = smp_processor_id(); + unsigned long flags; + int stuck = 50000; + + smp_invalidate_needed = cpu_online_map & (~(1< i386_endbase) + panic("smp_alloc_memory: Insufficient low memory for kernel trampoline 0x%lx.", mem_base); + trampoline_base = mem_base; + return mem_base + PAGE_SIZE; +} + +/* send a reschedule CPI to one CPU */ +void +smp_send_reschedule(int cpu) +{ + send_CPI_allbutself(VIC_RESCHEDULE_CPI); +} + +int +hard_smp_processor_id(void) +{ + __u8 i; + __u8 cpumask = inb(VIC_PROC_WHO_AM_I); + if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER) + return cpumask & 0x1F; + + for(i = 0; i < 8; i++) { + if(cpumask & (1<eip); + + if (!--prof_counter[cpu]) { + extern void update_one_process( struct task_struct *p, + unsigned long ticks, + unsigned long user, + unsigned long system, int cpu); + int user=0,system=0; + struct task_struct * p = current; + + /* + * After doing the above, we need to make like + * a normal interrupt - otherwise timer interrupts + * ignore the global interrupt lock, which is the + * WrongThing (tm) to do. + */ + + if (user_mode(regs)) + user=1; + else + system=1; + + irq_enter(cpu, 0); + update_one_process(p, 1, user, system, cpu); + if (p->pid) { + p->counter -= 1; + if (p->counter < 0) { + p->counter = 0; + p->need_resched = 1; + } + if (p->priority < DEF_PRIORITY) { + kstat.cpu_nice += user; + kstat.per_cpu_nice[cpu] += user; + } else { + kstat.cpu_user += user; + kstat.per_cpu_user[cpu] += user; + } + kstat.cpu_system += system; + kstat.per_cpu_system[cpu] += system; + + } + prof_counter[cpu]=prof_multiplier[cpu]; + irq_exit(cpu, 0); + } + + /* + * We take the 'long' return path, and there every subsystem + * grabs the apropriate locks (kernel lock/ irq lock). + * + * we might want to decouple profiling from the 'long path', + * and do the profiling totally in assembly. + * + * Currently this isn't too much of an issue (performance wise), + * we can take more than 100K local irqs per second on a 100 MHz P5. + */ + + if((++vic_tick[cpu] & 0x7) != 0) + return; + /* get here every 16 ticks (about every 1/6 of a second) */ + + /* Change our priority to give someone else a chance at getting + * the IRQ. The algorithm goes like this: + * + * In the VIC, the dynamically routed interrupt is always + * handled by the lowest priority eligible (i.e. receiving + * interrupts) CPU. If >1 eligible CPUs are equal lowest, the + * lowest processor number gets it. + * + * The priority of a CPU is controlled by a special per-CPU + * VIC priority register which is 3 bits wide 0 being lowest + * and 7 highest priority.. + * + * Therefore we subtract the average number of interrupts from + * the number we've fielded. If this number is negative, we + * lower the activity count and if it is positive, we raise + * it. + * + * I'm afraid this still leads to odd looking interrupt counts: + * the totals are all roughly equal, but the individual ones + * look rather skewed.*/ + weight = (vic_intr_count[cpu]*smp_num_cpus + - vic_intr_total) >> 4; + weight += 4; + if(weight > 7) + weight = 7; + if(weight < 0) + weight = 0; + + outb((__u8)weight, VIC_PRIORITY_REGISTER); + +#ifdef VOYAGER_DEBUG + if((vic_tick[cpu] & 0xFFF) == 0) { + /* print this message roughly every 25 secs */ + printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n", + cpu, vic_tick[cpu], weight); + } +#endif +} + +/* setup the profiling timer */ +int +setup_profiling_timer(unsigned int multiplier) +{ + return 0; +} + + +/* initialise the voyager interrupt gates + * + * This uses the macros in irq.h to set up assembly jump gates. The + * calls are then redirected to the same routine with smp_ prefixed */ +BUILD_SMP_INTERRUPT(vic_sys_interrupt) +BUILD_SMP_INTERRUPT(vic_cmn_interrupt) +BUILD_SMP_TIMER_INTERRUPT(vic_cpi_interrupt); + +/* The CPIs are handled in the per cpu 8259s, so they must be + * enabled to be received: FIX: enabling the CPIs in the early + * boot sequence interferes with bug checking; enable them later + * on in smp_init */ +#define VIC_SET_GATE(cpi, vector) \ + set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector)) + +void __init +voyager_smp_intr_init(void) +{ + int i; + + /* initialize the per cpu irq mask to all disabled */ + for(i = 0; i < NR_CPUS; i++) + vic_irq_mask[i] = 0xFFFF; + + VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt); + + VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt); + VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt); + + /* now put the VIC descriptor into the first 48 IRQs + * + * This is for later: first 16 correspond to PC IRQs; next 16 + * are Primary MC IRQs and final 16 are Secondary MC IRQs */ + for(i = 0; i < 48; i++) + irq_desc[i].handler = &vic_irq_type; +} + +/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per + * processor to recieve CPI */ +static void +send_CPI(__u32 cpuset, __u8 cpi) +{ + int i; + + if(cpi < VIC_START_FAKE_CPI) { + outb(cpuset, VIC_CPI_Registers[cpi]); + return; + } + for(i = 0; i < smp_num_cpus; i++) { + __u8 cpu = __cpu_logical_map[i]; + if(cpuset & (1<status & ~(IRQ_REPLAY | IRQ_WAITING); + action = NULL; + if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { + action = desc->action; + status |= IRQ_INPROGRESS; + } + else { + if(desc->status & IRQ_DISABLED) { + /* Damn, the interrupt actually + * arrived, do the lazy disable + * thing. */ + disable_local_vic_irq(irq); + ack_vic_irq(irq); + } + } + desc->status = status; + } + spin_unlock(&irq_controller_lock); + + /* Exit early if we were in progress or disabled. Note: no + * acknowledge of in progress interrupts since they will be + * ack'd as soon as the handler returns */ + if (!action) { + VDEBUG(("VOYAGER SMP: No Action for irq=%d, cpu=%d, flags=0x%x\n", + irq, cpu, desc->status)); + return; + } + handle_IRQ_event(irq, regs, action); + + spin_lock(&irq_controller_lock); + { + unsigned int status = desc->status & ~IRQ_INPROGRESS; +#ifdef VOYAGER_DEBUG + __u16 isr; +#endif + + desc->status = status; + if ((status & IRQ_DISABLED)) + disable_local_vic_irq(irq); +#ifdef VOYAGER_DEBUG + /* DEBUG: before we ack, check what's in progress */ + isr = vic_read_isr(); + if((isr & (1< +#ifdef CONFIG_VOYAGER +#include +#endif + #ifdef CONFIG_MAGIC_SYSRQ int sysrq_enabled = 1; #endif @@ -73,6 +77,12 @@ printk("Keyboard mode set to XLATE\n"); } break; +#ifdef CONFIG_VOYAGER + case 'c': + printk("VOYAGER DUMP\n"); + voyager_dump(); + break; +#endif /* CONFIG_VOYAGER */ #ifdef CONFIG_VT case 'k': /* K -- SAK */ printk("SAK\n"); Index: linux/2.2/include/asm-i386/smp.h diff -u linux/2.2/include/asm-i386/smp.h:1.1.1.1 linux/2.2/include/asm-i386/smp.h:1.1.1.1.56.1 --- linux/2.2/include/asm-i386/smp.h:1.1.1.1 Thu Mar 18 12:32:16 1999 +++ linux/2.2/include/asm-i386/smp.h Sat Feb 17 20:15:05 2001 @@ -16,6 +16,7 @@ #ifdef __SMP__ #ifndef ASSEMBLY +#include #include #include @@ -203,12 +204,13 @@ #define smp_processor_id() (current->processor) +#ifdef CONFIG_X86_LOCAL_APIC extern __inline int hard_smp_processor_id(void) { /* we don't want to mark this access volatile - bad code generation */ return GET_APIC_ID(*(unsigned long *)(APIC_BASE+APIC_ID)); } - +#endif #endif /* !ASSEMBLY */ #define NO_PROC_ID 0xFF /* No processor magic marker */ Index: linux/2.2/include/asm-i386/vic.h diff -u /dev/null linux/2.2/include/asm-i386/vic.h:1.1.10.1 --- /dev/null Sun Mar 4 11:35:56 2001 +++ linux/2.2/include/asm-i386/vic.h Sat Feb 17 20:15:05 2001 @@ -0,0 +1,56 @@ +/* Copyright 1999 NCR Corporation - Dayton, Ohio, USA + * + * Author: James.Bottomley@ColumbiaSC.ncr.com + * + * Standard include definitions for the NCR Voyager Interrupt Controller */ + +/* The eight CPI vectors. To activate a CPI, you write a bit mask + * corresponding to the processor set to be interrupted into the + * relevant register. That set of CPUs will then be interrupted with + * the CPI */ +static const int VIC_CPI_Registers[] = + {0xFC00, 0xFC01, 0xFC08, 0xFC09, + 0xFC10, 0xFC11, 0xFC18, 0xFC19 }; + +#define VIC_PROC_WHO_AM_I 0xfc29 +# define QUAD_IDENTIFIER 0xC0 +#define VIC_CPI_BASE_REGISTER 0xFC41 +#define VIC_PROCESSOR_ID 0xFC21 +# define VIC_CPU_MASQUERADE_ENABLE 0x8 + +#define VIC_CLAIM_REGISTER_0 0xFC38 +#define VIC_CLAIM_REGISTER_1 0xFC39 +#define VIC_REDIRECT_REGISTER_0 0xFC60 +#define VIC_REDIRECT_REGISTER_1 0xFC61 +#define VIC_PRIORITY_REGISTER 0xFC20 + +#define VIC_PRIMARY_MC_BASE 0xFC48 +#define VIC_SECONDARY_MC_BASE 0xFC49 + +/* this is where we place the CPI vectors */ +#define VIC_DEFAULT_CPI_BASE 0xC0 + +/* These define the CPIs we use in linux */ +#define VIC_CPI_LEVEL0 0 +#define VIC_CPI_LEVEL1 1 +/* now the fake CPIs */ +#define VIC_TIMER_CPI 2 +#define VIC_INVALIDATE_CPI 3 +#define VIC_RESCHEDULE_CPI 4 +#define VIC_STOP_CPU_CPI 5 +#define VIC_ENABLE_IRQ_CPI 6 + +#define VIC_START_FAKE_CPI VIC_TIMER_CPI +#define VIC_END_FAKE_CPI VIC_ENABLE_IRQ_CPI + +/* this is the SYS_INT CPI. */ +#define VIC_SYS_INT 8 +#define VIC_CMN_INT 15 + +/* This is the boot CPI for alternate processors. It gets overwritten + * by the above once the system has activated all available processors */ +#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL1 +#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL1 + 8) +#define VIC_BOOT_INTERRUPT_MASK 0xfd + +extern void smp_vic_timer_interrupt(struct pt_regs *regs); Index: linux/2.2/include/asm-i386/voyager.h diff -u /dev/null linux/2.2/include/asm-i386/voyager.h:1.1.10.1 --- /dev/null Sun Mar 4 11:35:56 2001 +++ linux/2.2/include/asm-i386/voyager.h Sat Feb 17 20:15:05 2001 @@ -0,0 +1,338 @@ +/* Copyright 1999 NCR Corporation - Dayton, Ohio, USA + * + * Author: James.Bottomley@ColumbiaSC.ncr.com + * + * Standard include definitions for the NCR Voyager system */ + +#undef VOYAGER_DEBUG + +#ifdef VOYAGER_DEBUG +#define VDEBUG(x) printk x +#else +#define VDEBUG(x) +#endif + +/* There are three levels of voyager machine: 3,4 and 5. The rule is + * if it's less than 3435 it's a Level 3 except for a 3360 which is + * a level 4. A 3435 or above is a Level 5 */ +#define VOYAGER_LEVEL5_AND_ABOVE 0x3435 +#define VOYAGER_LEVEL4 0x3360 + +/* voyager ports in standard I/O space */ +#define VOYAGER_MC_SETUP 0x96 + + +#define VOYAGER_CAT_CONFIG_PORT 0x97 +# define VOYAGER_CAT_DESELECT 0xff +#define VOYAGER_SSPB_RELOCATION_PORT 0x98 + +/* Valid CAT controller commands */ +/* start instruction register cycle */ +#define VOYAGER_CAT_IRCYC 0x01 +/* start data register cycle */ +#define VOYAGER_CAT_DRCYC 0x02 +/* move to execute state */ +#define VOYAGER_CAT_RUN 0x0F +/* end operation */ +#define VOYAGER_CAT_END 0x80 +/* hold in idle state */ +#define VOYAGER_CAT_HOLD 0x90 +/* single step an "intest" vector */ +#define VOYAGER_CAT_STEP 0xE0 +/* return cat controller to CLEMSON mode */ +#define VOYAGER_CAT_CLEMSON 0xFF + +/* the default cat command header */ +#define VOYAGER_CAT_HEADER 0x7F + +/* the range of possible CAT module ids in the system */ +#define VOYAGER_MIN_MODULE 0x10 +#define VOYAGER_MAX_MODULE 0x1f + +/* The voyager registers per asic */ +#define VOYAGER_ASIC_ID_REG 0x00 +#define VOYAGER_ASIC_TYPE_REG 0x01 +/* the sub address registers can be made auto incrementing on reads */ +#define VOYAGER_AUTO_INC_REG 0x02 +# define VOYAGER_AUTO_INC 0x04 +# define VOYAGER_NO_AUTO_INC 0xfb +#define VOYAGER_SUBADDRDATA 0x03 +#define VOYAGER_SCANPATH 0x05 +# define VOYAGER_CONNECT_ASIC 0x01 +# define VOYAGER_DISCONNECT_ASIC 0xfe + +/* the maximum size of a scan path -- used to form instructions */ +#define VOYAGER_MAX_SCAN_PATH 0x100 +/* the biggest possible register size (in bytes) */ +#define VOYAGER_MAX_REG_SIZE 4 + +/* Total number of possible modules (including submodules) */ +#define VOYAGER_MAX_MODULES 16 +/* Largest number of asics per module */ +#define VOYAGER_MAX_ASICS_PER_MODULE 7 + +/* the CAT asic of each module is always the first one */ +#define VOYAGER_CAT_ID 0 + +/* voyager instruction operations and registers */ +#define VOYAGER_READ_CONFIG 0x1 +#define VOYAGER_WRITE_CONFIG 0x2 +#define VOYAGER_BYPASS 0xff + +typedef struct voyager_asic +{ + __u8 asic_addr; /* ASIC address; Level 4 */ + __u8 asic_type; /* ASIC type */ + __u8 asic_id; /* ASIC id */ + __u8 jtag_id[4]; /* JTAG id */ + __u8 asic_location; /* Location within scan path; start w/ 0 */ + __u8 bit_location; /* Location within bit stream; start w/ 0 */ + __u8 ireg_length; /* Instruction register length */ + __u16 subaddr; /* Amount of sub address space */ + struct voyager_asic *next; /* Next asic in linked list */ +} voyager_asic_t; + +typedef struct voyager_module { + __u8 module_addr; /* Module address */ + __u8 spc; /* Scan path connected */ + __u16 ee_size; /* Size of the EEPROM */ + __u16 num_asics; /* Number of Asics */ + __u16 inst_bits; /* Instruction bits in the scan path */ + __u16 largest_reg; /* Largest register in the scan path */ + __u16 smallest_reg; /* Smallest register in the scan path */ + voyager_asic_t *asic; /* First ASIC in scan path (CAT_I) */ + struct voyager_module *submodule; /* Submodule pointer */ + struct voyager_module *next; /* Next module in linked list */ +} voyager_module_t; + +typedef struct voyager_eeprom_hdr { + __u8 module_id[4] __attribute__((packed)); + __u8 version_id __attribute__((packed)); + __u8 config_id __attribute__((packed)); + __u16 boundry_id __attribute__((packed)); /* boundary scan id */ + __u16 ee_size __attribute__((packed)); /* size of EEPROM */ + __u8 assembly[11] __attribute__((packed)); /* assembly # */ + __u8 assembly_rev __attribute__((packed)); /* assembly rev */ + __u8 tracer[4] __attribute__((packed)); /* tracer number */ + __u16 assembly_cksum __attribute__((packed)); /* asm checksum */ + __u16 power_consump __attribute__((packed)); /* pwr requirements */ + __u16 num_asics __attribute__((packed)); /* number of asics */ + __u16 bist_time __attribute__((packed)); /* min. bist time */ + __u16 err_log_offset __attribute__((packed)); /* error log offset */ + __u16 scan_path_offset __attribute__((packed));/* scan path offset */ + __u16 cct_offset __attribute__((packed)); + __u16 log_length __attribute__((packed)); /* length of err log */ + __u16 xsum_end __attribute__((packed)); /* offset to end of + checksum */ + __u8 reserved[4] __attribute__((packed)); + __u8 sflag __attribute__((packed)); /* starting sentinal */ + __u8 part_number[13] __attribute__((packed)); /* prom part number */ + __u8 version[10] __attribute__((packed)); /* version number */ + __u8 signature[8] __attribute__((packed)); + __u16 eeprom_chksum __attribute__((packed)); + __u32 data_stamp_offset __attribute__((packed)); + __u8 eflag __attribute__((packed)); /* ending sentinal */ +} voyager_eprom_hdr_t; + + + +#define VOYAGER_EPROM_SIZE_OFFSET ((__u16)(&(((voyager_eprom_hdr_t *)0)->ee_size))) + +/* the following three definitions are for internal table layouts + * in the module EPROMs. We really only care about the IDs and + * offsets */ +typedef struct voyager_sp_table { + __u8 asic_id __attribute__((packed)); + __u8 bypass_flag __attribute__((packed)); + __u16 asic_data_offset __attribute__((packed)); + __u16 config_data_offset __attribute__((packed)); +} voyager_sp_table_t; + +typedef struct voyager_jtag_table { + __u8 icode[4] __attribute__((packed)); + __u8 runbist[4] __attribute__((packed)); + __u8 intest[4] __attribute__((packed)); + __u8 samp_preld[4] __attribute__((packed)); + __u8 ireg_len __attribute__((packed)); +} voyager_jtt_t; + +typedef struct voyager_asic_data_table { + __u8 jtag_id[4] __attribute__((packed)); + __u16 length_bsr __attribute__((packed)); + __u16 length_bist_reg __attribute__((packed)); + __u32 bist_clk __attribute__((packed)); + __u16 subaddr_bits __attribute__((packed)); + __u16 seed_bits __attribute__((packed)); + __u16 sig_bits __attribute__((packed)); + __u16 jtag_offset __attribute__((packed)); +} voyager_at_t; + +/* Voyager Interrupt Controller (VIC) registers */ + +/* Base to add to Cross Processor Interrupts (CPIs) when triggering + * the CPU IRQ line */ +/* register defines for the WCBICs (one per processor) */ +#define VOYAGER_WCBIC0 0x41 /* bus A node P1 processor 0 */ +#define VOYAGER_WCBIC1 0x49 /* bus A node P1 processor 1 */ +#define VOYAGER_WCBIC2 0x51 /* bus A node P2 processor 0 */ +#define VOYAGER_WCBIC3 0x59 /* bus A node P2 processor 1 */ +#define VOYAGER_WCBIC4 0x61 /* bus B node P1 processor 0 */ +#define VOYAGER_WCBIC5 0x69 /* bus B node P1 processor 1 */ +#define VOYAGER_WCBIC6 0x71 /* bus B node P2 processor 0 */ +#define VOYAGER_WCBIC7 0x79 /* bus B node P2 processor 1 */ + + +/* top of memory registers */ +#define VOYAGER_WCBIC_TOM_L 0x4 +#define VOYAGER_WCBIC_TOM_H 0x5 + +/* register defines for Voyager Memory Contol (VMC) + * these are present on L4 machines only */ +#define VOYAGER_VMC1 0x81 +#define VOYAGER_VMC2 0x91 +#define VOYAGER_VMC3 0xa1 +#define VOYAGER_VMC4 0xb1 + +/* VMC Ports */ +#define VOYAGER_VMC_MEMORY_SETUP 0x9 +# define VMC_Interleaving 0x01 +# define VMC_4Way 0x02 +# define VMC_EvenCacheLines 0x04 +# define VMC_HighLine 0x08 +# define VMC_Start0_Enable 0x20 +# define VMC_Start1_Enable 0x40 +# define VMC_Vremap 0x80 +#define VOYAGER_VMC_BANK_DENSITY 0xa +# define VMC_BANK_EMPTY 0 +# define VMC_BANK_4MB 1 +# define VMC_BANK_16MB 2 +# define VMC_BANK_64MB 3 +# define VMC_BANK0_MASK 0x03 +# define VMC_BANK1_MASK 0x0C +# define VMC_BANK2_MASK 0x30 +# define VMC_BANK3_MASK 0xC0 + +/* Magellan Memory Controller (MMC) defines - present on L5 */ +#define VOYAGER_MMC_ASIC_ID 1 +/* the two memory modules corresponding to memory cards in the system */ +#define VOYAGER_MMC_MEMORY0_MODULE 0x14 +#define VOYAGER_MMC_MEMORY1_MODULE 0x15 +/* the Magellan Memory Address (MMA) defines */ +#define VOYAGER_MMA_ASIC_ID 2 + +/* Useful areas in extended CMOS */ +#define VOYAGER_PROCESSOR_PRESENT_MASK 0x88a +#define VOYAGER_MEMORY_CLICKMAP 0xa23 + +/* SUS In Control bit - used to tell SUS that we don't need to be + * babysat anymore */ +#define VOYAGER_SUS_IN_CONTROL_PORT 0x3ff +# define VOYAGER_IN_CONTROL_FLAG 0x80 + + +struct voyager_bios_info { + __u8 len; + __u8 major; + __u8 minor; + __u8 debug; + __u8 num_classes; + __u8 class_1; + __u8 class_2; +}; + +/* The following structures and definitions are for the Kernel/SUS + * interface these are needed to find out how SUS initialised any Quad + * boards in the system */ + +#define NUMBER_OF_MC_BUSSES 2 +#define SLOTS_PER_MC_BUS 8 +#define MAX_CPUS 16 /* 16 way CPU system */ +#define MAX_PROCESSOR_BOARDS 4 /* 4 processor slot system */ +#define MAX_CACHE_LEVELS 4 /* # of cache levels supported */ +#define MAX_SHARED_CPUS 4 /* # of CPUs that can share a LARC */ +#define NUMBER_OF_POS_REGS 8 + +typedef struct { + __u8 MC_Slot __attribute__((packed)); + __u8 POS_Values[NUMBER_OF_POS_REGS] __attribute__((packed)); +} MC_SlotInformation_t; + +struct QuadDescription { + __u8 Type __attribute__((packed)); /* for type 0 (DYADIC or MONADIC) all fields + * will be zero except for slot */ + __u8 StructureVersion __attribute__((packed)); + __u32 CPI_BaseAddress __attribute__((packed)); + __u32 LARC_BankSize __attribute__((packed)); + __u32 LocalMemoryStateBits __attribute__((packed)); + __u8 Slot __attribute__((packed)); /* Processor slots 1 - 4 */ +}; + +struct ProcBoardInfo { + __u8 Type __attribute__((packed)); + __u8 StructureVersion __attribute__((packed)); + __u8 NumberOfBoards __attribute__((packed)); + struct QuadDescription QuadData[MAX_PROCESSOR_BOARDS] __attribute__((packed)); +}; + +struct CacheDescription { + __u8 Level __attribute__((packed)); + __u32 TotalSize __attribute__((packed)); + __u16 LineSize __attribute__((packed)); + __u8 Associativity __attribute__((packed)); + __u8 CacheType __attribute__((packed)); + __u8 WriteType __attribute__((packed)); + __u8 Number_CPUs_SharedBy __attribute__((packed)); + __u8 Shared_CPUs_Hardware_IDs[MAX_SHARED_CPUS] __attribute__((packed)); + +}; + +struct CPU_Description { + __u8 CPU_HardwareId __attribute__((packed)); + char *FRU_String __attribute__((packed)); + __u8 NumberOfCacheLevels __attribute__((packed)); + struct CacheDescription CacheLevelData[MAX_CACHE_LEVELS] __attribute__((packed)); +}; + +struct CPU_Info { + __u8 Type __attribute__((packed)); + __u8 StructureVersion __attribute__((packed)); + __u8 NumberOf_CPUs __attribute__((packed)); + struct CPU_Description CPU_Data[MAX_CPUS] __attribute__((packed)); +}; + + +/* + * This structure will be used by SUS and the OS. + * The assumption about this structure is that no blank space is + * packed in it by our friend the compiler. + */ +typedef struct { + __u8 Mailbox_SUS; /* Written to by SUS to give commands/response to the OS */ + __u8 Mailbox_OS; /* Written to by the OS to give commands/response to SUS */ + __u8 SUS_MailboxVersion; /* Tells the OS which iteration of the interface SUS supports */ + __u8 OS_MailboxVersion; /* Tells SUS which iteration of the interface the OS supports */ + __u32 OS_Flags; /* Flags set by the OS as info for SUS */ + __u32 SUS_Flags; /* Flags set by SUS as info for the OS */ + __u32 WatchDogPeriod; /* Watchdog period (in seconds) which the DP uses to see if the OS is dead */ + __u32 WatchDogCount; /* Updated by the OS on every tic. */ + __u32 MemoryFor_SUS_ErrorLog; /* Flat 32 bit address which tells SUS where to stuff the SUS error log on a dump */ + MC_SlotInformation_t MC_SlotInfo[NUMBER_OF_MC_BUSSES*SLOTS_PER_MC_BUS]; /* Storage for MCA POS data */ + /* All new SECOND_PASS_INTERFACE fields added from this point */ + struct ProcBoardInfo *BoardData; + struct CPU_Info *CPU_Data; + /* All new fields must be added from this point */ +} Voyager_KernelSUS_Mbox_t; + + +/* functions exported by the voyager and voyager_smp modules */ + +extern int voyager_cat_readb(__u8 module, __u8 asic, int reg); +extern void voyager_cat_init(void); +extern void voyager_trap_init(void); +extern void voyager_setup_irqs(void); +extern __u32 voyager_memory_detect(void); +extern void voyager_smp_intr_init(void); +extern __u8 voyager_extended_cmos_read(__u16 cmos_address); +extern void voyager_dump(void); +extern void voyager_smp_dump(void); +extern void voyager_timer_interrupt(struct pt_regs *regs);