This BitKeeper patch contains the following changesets: jejb@mulgrave.(none)|ChangeSet|20020312001709|20252 jejb@mulgrave.(none)|ChangeSet|20020311234733|20271 jejb@mulgrave.(none)|ChangeSet|20020311224513|41298 jejb@mulgrave.(none)|ChangeSet|20020311221916|41310 jejb@mulgrave.(none)|ChangeSet|20020311213008|41291 jejb@mulgrave.(none)|ChangeSet|20020311185301|41281 jejb@mulgrave.(none)|ChangeSet|20020311184444|29086 jejb@mulgrave.(none)|ChangeSet|20020311063131|29096 jejb@mulgrave.(none)|ChangeSet|20020311062143|16023 jejb@mulgrave.(none)|ChangeSet|20020311060259|02667 jejb@mulgrave.(none)|ChangeSet|20020311053436|02666 jejb@mulgrave.(none)|ChangeSet|20020311035412|41918 jejb@mulgrave.(none)|ChangeSet|20020311033237|03207 jejb@mulgrave.(none)|ChangeSet|20020311031530|23441 jejb@malley.hansenpartnership.com|ChangeSet|20020227205607|05141 jejb@mulgrave.(none)|ChangeSet|20020227154608|03079 jejb@mulgrave.(none)|ChangeSet|20020227153807|03086 jejb@mulgrave.(none)|ChangeSet|20020227153222|03091 jejb@mulgrave.(none)|ChangeSet|20020224163852|61249 jejb@mulgrave.(none)|ChangeSet|20020224163312|61235 jejb@mulgrave.(none)|ChangeSet|20020224161953|41872 jejb@mulgrave.(none)|ChangeSet|20020224161137|41852 jejb@mulgrave.(none)|ChangeSet|20020224155559|27107 jejb@mulgrave.(none)|ChangeSet|20020224154639|28501 jejb@mulgrave.(none)|ChangeSet|20020224152223|16173 jejb@mulgrave.(none)|ChangeSet|20020224151539|16175 jejb@mulgrave.(none)|ChangeSet|20020224145459|21941 jejb@mulgrave.(none)|ChangeSet|20020224144114|23329 jejb@mulgrave.(none)|ChangeSet|20020224140429|10299 # ID: torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 # User: jejb # Host: mulgrave.(none) # Root: /home/jejb/BK/voyager-2.5 # Patch vers: 1.3 # Patch type: REGULAR == ChangeSet == torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 torvalds@athlon.transmeta.com|ChangeSet|20020205235759|62270 D 1.134.1.1 02/02/24 08:04:29-06:00 jejb@mulgrave.(none) +22 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add support for the NCR Voyager architecture c c A microchannel (MCA) SMP system capable of going up to 32 CPUs and c taking anything from an i486 to a PPro as the CPUs c c Voyager architectures are machine classes: c c 3430/3360/345x/35xx/4100/51xx K 10299 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224140213|00548 > torvalds@athlon.transmeta.com|include/asm-i386/hw_irq.h|20020205173944|02324|3649a38c193ce3f jejb@mulgrave.(none)|include/asm-i386/hw_irq.h|20020224140213|35432 > torvalds@athlon.transmeta.com|Documentation/Configure.help|20020205174036|10200|b2e6fcb151e0e36d jejb@mulgrave.(none)|Documentation/Configure.help|20020224140212|31895 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140214|03482 > jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140213|49808|ac03dc9d49350595 jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140214|40442 > jejb@mulgrave.(none)|Documentation/voyager.txt|20020224140213|45547|2abd64f1ad30186d jejb@mulgrave.(none)|Documentation/voyager.txt|20020224140214|31612 > jejb@mulgrave.(none)|include/asm-i386/voyager.h|20020224140213|60867|30e452a4faa1582f jejb@mulgrave.(none)|include/asm-i386/voyager.h|20020224140214|19261 > torvalds@athlon.transmeta.com|drivers/char/sysrq.c|20020205174004|19337|54afe09e7d33cfce jejb@mulgrave.(none)|drivers/char/sysrq.c|20020224140213|40686 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020224140213|53996 > torvalds@athlon.transmeta.com|include/asm-i386/smp.h|20020205173944|41674|b06e3b553054c2ec jejb@mulgrave.(none)|include/asm-i386/smp.h|20020224140213|24171 > torvalds@athlon.transmeta.com|arch/i386/kernel/i8259.c|20020205174021|59798|fc99768517501f14 jejb@mulgrave.(none)|arch/i386/kernel/i8259.c|20020224140213|34319 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020224140213|28985 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020224140213|16892 > jejb@mulgrave.(none)|include/asm-i386/vic.h|20020224140213|59289|a22c1f9c53cd3c50 jejb@mulgrave.(none)|include/asm-i386/vic.h|20020224140214|33701 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_thread.c|20020224140213|55199|411f897383390efd jejb@mulgrave.(none)|arch/i386/kernel/voyager_thread.c|20020224140214|58225 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_cat.c|20020224140213|51425|4afbdd55fedc3919 jejb@mulgrave.(none)|arch/i386/kernel/voyager_cat.c|20020224140214|52200 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020224140212|04150 > torvalds@athlon.transmeta.com|arch/i386/boot/setup.S|20020205174020|11654|60d81ba2278e7f2f jejb@mulgrave.(none)|arch/i386/boot/setup.S|20020224140213|13975 > torvalds@athlon.transmeta.com|arch/i386/kernel/irq.c|20020205174021|53161|b0f85cd930bb690b jejb@mulgrave.(none)|arch/i386/kernel/irq.c|20020224140213|52532 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020224140213|43384 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020224140213|00430 > torvalds@athlon.transmeta.com|arch/i386/kernel/i386_ksyms.c|20020205174021|57868|87ffcb8a3a553b23 jejb@mulgrave.(none)|arch/i386/kernel/i386_ksyms.c|20020224140213|53301 torvalds@athlon.transmeta.com|ChangeSet|20020205235917|09745 D 1.146.1.1 02/02/24 08:41:14-06:00 jejb@mulgrave.(none) +6 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Standard manual merge to contain kernel changes i jejb@mulgrave.(none)|ChangeSet|20020224140429|10299 K 23329 M jejb@mulgrave.(none)|ChangeSet|20020224140429|10299 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224144114|15586 > torvalds@athlon.transmeta.com|drivers/char/sysrq.c|20020205174004|19337|54afe09e7d33cfce jejb@mulgrave.(none)|drivers/char/sysrq.c|20020224144114|41366 > torvalds@athlon.transmeta.com|Documentation/Configure.help|20020205174036|10200|b2e6fcb151e0e36d jejb@mulgrave.(none)|Documentation/Configure.help|20020224144114|46853 > torvalds@athlon.transmeta.com|arch/i386/kernel/irq.c|20020205174021|53161|b0f85cd930bb690b jejb@mulgrave.(none)|arch/i386/kernel/irq.c|20020224144114|57046 > torvalds@athlon.transmeta.com|arch/i386/boot/setup.S|20020205174020|11654|60d81ba2278e7f2f jejb@mulgrave.(none)|arch/i386/boot/setup.S|20020224144114|14017 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020224144114|08953 jejb@mulgrave.(none)|ChangeSet|20020224144114|23329 D 1.146.1.2 02/02/24 08:54:59-06:00 jejb@mulgrave.(none) +13 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Voyager update c c - Clean up code on feedback from Dave Jones and Rik van Riel. c - Correct timer interrupt handler imbalance that was causing c system vs user cpu timings to be off K 21941 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224145423|34057 > torvalds@athlon.transmeta.com|Documentation/Configure.help|20020205174036|10200|b2e6fcb151e0e36d jejb@mulgrave.(none)|Documentation/Configure.help|20020224145422|47097 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224145423|30520 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020224145423|51479 > jejb@mulgrave.(none)|Documentation/voyager.txt|20020224140213|45547|2abd64f1ad30186d jejb@mulgrave.(none)|Documentation/voyager.txt|20020224145423|44263 > jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140213|49808|ac03dc9d49350595 jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224145423|04496 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020224145423|41507 > torvalds@athlon.transmeta.com|arch/i386/kernel/i8259.c|20020205174021|59798|fc99768517501f14 jejb@mulgrave.(none)|arch/i386/kernel/i8259.c|20020224145423|09102 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020224145423|33431 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020224145423|19287 > torvalds@athlon.transmeta.com|arch/i386/kernel/irq.c|20020205174021|53161|b0f85cd930bb690b jejb@mulgrave.(none)|arch/i386/kernel/irq.c|20020224145423|57014 > torvalds@athlon.transmeta.com|include/asm-i386/irq.h|20020205173944|23037|cfa60afe4ac0a973 jejb@mulgrave.(none)|include/asm-i386/irq.h|20020224145423|18853 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020224145423|41509 torvalds@athlon.transmeta.com|ChangeSet|20020206001333|03877 D 1.158.1.1 02/02/24 09:15:39-06:00 jejb@mulgrave.(none) +9 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020224144114|23329 i jejb@mulgrave.(none)|ChangeSet|20020224145459|21941 K 16175 M jejb@mulgrave.(none)|ChangeSet|20020224145459|21941 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020224151538|26260 > torvalds@athlon.transmeta.com|Documentation/Configure.help|20020205174036|10200|b2e6fcb151e0e36d jejb@mulgrave.(none)|Documentation/Configure.help|20020224151538|25250 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020224151539|47397 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020224151539|47403 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020224151539|36762 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224151539|62780 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020224151539|48361 > torvalds@athlon.transmeta.com|drivers/char/sysrq.c|20020205174004|19337|54afe09e7d33cfce jejb@mulgrave.(none)|drivers/char/sysrq.c|20020224151539|41686 > torvalds@athlon.transmeta.com|include/asm-i386/smp.h|20020205173944|41674|b06e3b553054c2ec jejb@mulgrave.(none)|include/asm-i386/smp.h|20020224151539|59148 jejb@mulgrave.(none)|ChangeSet|20020224151539|16175 D 1.158.1.2 02/02/24 09:22:23-06:00 jejb@mulgrave.(none) +2 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Voyager architecture c c - basic upports: ignore hyperthreading and change init task setup c - add cache alignment to certain internal arrays K 16173 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224152203|65324 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224152203|49861 torvalds@athlon.transmeta.com|ChangeSet|20020206001849|15802 D 1.167.2.1 02/02/24 09:46:39-06:00 jejb@mulgrave.(none) +11 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020224151539|16175 i jejb@mulgrave.(none)|ChangeSet|20020224152223|16173 K 28501 M jejb@mulgrave.(none)|ChangeSet|20020224152223|16173 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020224154638|26203 > torvalds@athlon.transmeta.com|Documentation/Configure.help|20020205174036|10200|b2e6fcb151e0e36d jejb@mulgrave.(none)|BitKeeper/deleted/.del-Configure.help~b2e6fcb151e0e36d|20020224154639|29225 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020224154639|63027 > torvalds@athlon.transmeta.com|arch/i386/boot/setup.S|20020205174020|11654|60d81ba2278e7f2f jejb@mulgrave.(none)|arch/i386/boot/setup.S|20020224154639|26459 > torvalds@athlon.transmeta.com|arch/i386/kernel/i8259.c|20020205174021|59798|fc99768517501f14 jejb@mulgrave.(none)|arch/i386/kernel/i8259.c|20020224154639|08622 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020224154639|36051 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020224154639|42081 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224154639|01130 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020224154639|03309 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020224154639|38021 > torvalds@athlon.transmeta.com|include/asm-i386/hw_irq.h|20020205173944|02324|3649a38c193ce3f jejb@mulgrave.(none)|include/asm-i386/hw_irq.h|20020224154639|02606 jejb@mulgrave.(none)|ChangeSet|20020224154639|28501 D 1.167.2.2 02/02/24 09:55:59-06:00 jejb@mulgrave.(none) +6 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Voyager changes c c - follow help spit c - add smp migration interrupt for new scheduler c - correct logical_cpu bug in hardirq.h (only shows when phys and c logical cpu numbers are different) K 27107 P ChangeSet ------------------------------------------------ 0a0 > jejb@mulgrave.(none)|include/asm-i386/vic.h|20020224140213|59289|a22c1f9c53cd3c50 jejb@mulgrave.(none)|include/asm-i386/vic.h|20020224155525|42897 > torvalds@athlon.transmeta.com|include/asm-i386/hardirq.h|20020205173944|59272|15265640a13d83ce jejb@mulgrave.(none)|include/asm-i386/hardirq.h|20020224155525|54521 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224155525|29598 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020224155525|17395 > patch@athlon.transmeta.com|arch/i386/Config.help|20020206001713|03723|3a650f5e40e2823a jejb@mulgrave.(none)|arch/i386/Config.help|20020224155525|04710 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020224155525|26390 torvalds@home.transmeta.com|ChangeSet|20020211032403|18448 D 1.262.12.1 02/02/24 10:11:37-06:00 jejb@mulgrave.(none) +10 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020224154639|28501 i jejb@mulgrave.(none)|ChangeSet|20020224155559|27107 K 41852 M jejb@mulgrave.(none)|ChangeSet|20020224155559|27107 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020224161137|44720 > patch@athlon.transmeta.com|arch/i386/Config.help|20020206001713|03723|3a650f5e40e2823a jejb@mulgrave.(none)|arch/i386/Config.help|20020224161137|31700 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020224161137|03971 > torvalds@athlon.transmeta.com|arch/i386/kernel/irq.c|20020205174021|53161|b0f85cd930bb690b jejb@mulgrave.(none)|arch/i386/kernel/irq.c|20020224161137|56962 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020224161137|01825 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224161137|03045 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020224161137|23210 > torvalds@athlon.transmeta.com|include/asm-i386/hardirq.h|20020205173944|59272|15265640a13d83ce jejb@mulgrave.(none)|include/asm-i386/hardirq.h|20020224161137|58487 > torvalds@athlon.transmeta.com|include/asm-i386/hw_irq.h|20020205173944|02324|3649a38c193ce3f jejb@mulgrave.(none)|include/asm-i386/hw_irq.h|20020224161137|20806 > torvalds@athlon.transmeta.com|include/asm-i386/smp.h|20020205173944|41674|b06e3b553054c2ec jejb@mulgrave.(none)|include/asm-i386/smp.h|20020224161137|60479 jejb@mulgrave.(none)|ChangeSet|20020224161137|41852 D 1.262.12.2 02/02/24 10:19:53-06:00 jejb@mulgrave.(none) +4 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Voyager updates c c - Alter thread start up model (from smpboot.c) c - change CPI spinlock types to _raw to prevent pre-emption during CPI c - change kvoyagerd wait from completion to semaphore to correct c problem where kvoyagerd in D wait contributes 1 to load average. K 41872 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020224161909|06979 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_thread.c|20020224140213|55199|411f897383390efd jejb@mulgrave.(none)|arch/i386/kernel/voyager_thread.c|20020224161909|01250 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224161909|31720 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_cat.c|20020224140213|51425|4afbdd55fedc3919 jejb@mulgrave.(none)|arch/i386/kernel/voyager_cat.c|20020224161909|50720 torvalds@penguin.transmeta.com|ChangeSet|20020220020710|36335 D 1.369.11.1 02/02/24 10:33:12-06:00 jejb@mulgrave.(none) +6 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020224161137|41852 i jejb@mulgrave.(none)|ChangeSet|20020224161953|41872 K 61235 M jejb@mulgrave.(none)|ChangeSet|20020224161953|41872 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020224163312|54875 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020224163312|29211 > torvalds@athlon.transmeta.com|arch/i386/kernel/i386_ksyms.c|20020205174021|57868|87ffcb8a3a553b23 jejb@mulgrave.(none)|arch/i386/kernel/i386_ksyms.c|20020224163312|49625 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020224163312|12661 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020224163312|58026 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020224163312|16847 jejb@mulgrave.(none)|ChangeSet|20020224163312|61235 D 1.369.11.2 02/02/24 10:38:52-06:00 jejb@mulgrave.(none) +2 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Voyager changes c c - upport: remove unnecessary zeroing of cpuinfo c - change missed completion to semaphore K 61249 P ChangeSet ------------------------------------------------ 0a0 > jejb@mulgrave.(none)|include/asm-i386/voyager.h|20020224140213|60867|30e452a4faa1582f jejb@mulgrave.(none)|include/asm-i386/voyager.h|20020224163815|19031 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224163815|25357 torvalds@penguin.transmeta.com|ChangeSet|20020227010121|41793 D 1.375.1.48 02/02/27 09:32:22-06:00 jejb@mulgrave.(none) +5 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020224163312|61235 i jejb@mulgrave.(none)|ChangeSet|20020224163852|61249 K 3091 M jejb@mulgrave.(none)|ChangeSet|20020224163852|61249 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020227153037|11438 > torvalds@athlon.transmeta.com|arch/i386/kernel/i8259.c|20020205174021|59798|fc99768517501f14 jejb@mulgrave.(none)|arch/i386/kernel/i8259.c|20020227153222|08622 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020227153038|61178 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020227153038|40053 > torvalds@athlon.transmeta.com|include/asm-i386/hw_irq.h|20020205173944|02324|3649a38c193ce3f jejb@mulgrave.(none)|include/asm-i386/hw_irq.h|20020227153038|18128 jejb@mulgrave.(none)|ChangeSet|20020227153222|03091 D 1.375.1.49 02/02/27 09:38:07-06:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Update smp interrupt abstraction c c - merge changes from 1.373 (removal of task migration IPI) K 3086 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020227153711|02761 jejb@mulgrave.(none)|ChangeSet|20020227153807|03086 D 1.375.1.50 02/02/27 09:46:08-06:00 jejb@mulgrave.(none) +2 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Voyager c c remove CPIs associated with process migration as per change c set 1.373 K 3079 P ChangeSet ------------------------------------------------ 0a0 > jejb@mulgrave.(none)|include/asm-i386/vic.h|20020224140213|59289|a22c1f9c53cd3c50 jejb@mulgrave.(none)|include/asm-i386/vic.h|20020227154608|36121 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020227154608|63592 jejb@mulgrave.(none)|ChangeSet|20020227154608|03079 D 1.375.1.51 02/02/27 14:56:07-06:00 jejb@malley.hansenpartnership.com +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Fix new SMP migration thread code (introduced in change set 1.373) c c - make migration_mask a logical bitmap with correct conversions. K 5141 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|kernel/sched.c|20020205173939|47232|5bb23172c60d3e93 jejb@malley.hansenpartnership.com|kernel/sched.c|20020227205530|16801 jejb@malley.hansenpartnership.com|ChangeSet|20020227205607|05141 D 1.375.1.52 02/03/10 22:15:30-05:00 jejb@mulgrave.(none) +4 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge ssh://james/BK/voyager-2.5 c into mulgrave.(none):/home/jejb/BK/voyager-2.5 i jgarzik@mandrakesoft.com|ChangeSet|20020227191402|41642 i jgarzik@mandrakesoft.com|ChangeSet|20020227234828|44363 i elenstev@mesatop.com|ChangeSet|20020228000840|44502 i elenstev@mesatop.com|ChangeSet|20020228002026|43932 i fero@sztalker.hu|ChangeSet|20020228003547|42960 i torvalds@penguin.transmeta.com|ChangeSet|20020228054506|44412 i torvalds@penguin.transmeta.com|ChangeSet|20020228055049|47681 i torvalds@penguin.transmeta.com|ChangeSet|20020228201156|48000 i dalecki@evision-ventures.com|ChangeSet|20020228201512|48086 i dalecki@evision-ventures.com|ChangeSet|20020228201518|50730 i dalecki@evision-ventures.com|ChangeSet|20020228201525|54306 i dalecki@evision-ventures.com|ChangeSet|20020228201530|54317 i dalecki@evision-ventures.com|ChangeSet|20020228201537|54534 i twaugh@redhat.com|ChangeSet|20020228201919|54538 i twaugh@redhat.com|ChangeSet|20020228201924|54542 i twaugh@redhat.com|ChangeSet|20020228201929|53672 i twaugh@redhat.com|ChangeSet|20020228201934|53174 i viro@math.psu.edu|ChangeSet|20020228202333|47280 i viro@math.psu.edu|ChangeSet|20020228202339|47680 i viro@math.psu.edu|ChangeSet|20020228202344|46253 i viro@math.psu.edu|ChangeSet|20020228202349|46258 i viro@math.psu.edu|ChangeSet|20020228202355|46506 i viro@math.psu.edu|ChangeSet|20020228202400|44941 i viro@math.psu.edu|ChangeSet|20020228202405|45344 i viro@math.psu.edu|ChangeSet|20020228202415|44606 i torvalds@penguin.transmeta.com|ChangeSet|20020228202720|43135 i torvalds@penguin.transmeta.com|ChangeSet|20020228203210|42601 i kraxel@bytesex.org|ChangeSet|20020228203436|43737 i torvalds@penguin.transmeta.com|ChangeSet|20020228204511|44206 i torvalds@penguin.transmeta.com|ChangeSet|20020228210201|45998 i torvalds@penguin.transmeta.com|ChangeSet|20020228211804|36274 i shaggy@austin.ibm.com|ChangeSet|20020228212251|35469 i torvalds@penguin.transmeta.com|ChangeSet|20020301003732|35453 i torvalds@penguin.transmeta.com|ChangeSet|20020301041020|34913 i viro@math.psu.edu|ChangeSet|20020302213008|33565 i viro@math.psu.edu|ChangeSet|20020302213013|32181 i viro@math.psu.edu|ChangeSet|20020302213033|32537 i rusty@rustcorp.com.au|ChangeSet|20020302213247|31842 i rusty@rustcorp.com.au|ChangeSet|20020302213252|31092 i rusty@rustcorp.com.au|ChangeSet|20020302213258|19869 i torvalds@penguin.transmeta.com|ChangeSet|20020302213603|18139 i torvalds@penguin.transmeta.com|ChangeSet|20020302214111|53253 i jaharkes@cs.cmu.edu|ChangeSet|20020302214154|54331 i david-b@pacbell.net|ChangeSet|20020302214546|53056 i bcrl@toomuch.toronto.redhat.com|ChangeSet|20020303205259|58283 i bcrl@toomuch.toronto.redhat.com|ChangeSet|20020304162205|58279 i torvalds@penguin.transmeta.com|ChangeSet|20020305231217|61278 i adam@nmt.edu|ChangeSet|20020305231617|58432 i Andries.Brouwer@cwi.nl|ChangeSet|20020305231818|57025 i rml@tech9.net|ChangeSet|20020305231934|56098 i torvalds@penguin.transmeta.com|ChangeSet|20020305232930|56362 i viro@math.psu.edu|ChangeSet|20020306032442|56387 i torvalds@penguin.transmeta.com|ChangeSet|20020307002231|59109 i torvalds@penguin.transmeta.com|ChangeSet|20020307002530|60946 i viro@math.psu.edu|ChangeSet|20020307002720|60937 i torvalds@penguin.transmeta.com|ChangeSet|20020307004623|63450 i dalecki@evision-ventures.com|ChangeSet|20020307004905|63776 K 23441 M dalecki@evision-ventures.com|ChangeSet|20020307004905|63776 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020311031528|43299 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020311031529|03419 > torvalds@athlon.transmeta.com|drivers/char/sysrq.c|20020205174004|19337|54afe09e7d33cfce jejb@mulgrave.(none)|drivers/char/sysrq.c|20020311031529|42078 > torvalds@athlon.transmeta.com|kernel/sched.c|20020205173939|47232|5bb23172c60d3e93 jejb@mulgrave.(none)|kernel/sched.c|20020311031529|23476 jejb@mulgrave.(none)|ChangeSet|20020311031530|23441 D 1.375.1.53 02/03/10 22:32:37-05:00 jejb@mulgrave.(none) +7 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge (tidy up later) i jejb@mulgrave.(none)|ChangeSet|20020310223507|42825 i jejb@mulgrave.(none)|ChangeSet|20020311001639|42829 i jejb@mulgrave.(none)|ChangeSet|20020311030012|43984 K 3207 M jejb@mulgrave.(none)|ChangeSet|20020311030012|43984 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020311032744|05933 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020311033237|14964 > torvalds@athlon.transmeta.com|arch/i386/kernel/i8259.c|20020205174021|59798|fc99768517501f14 jejb@mulgrave.(none)|arch/i386/kernel/i8259.c|20020311033236|42500 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311033236|23360 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311032744|60640 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311033237|11189 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311032743|40267 jejb@mulgrave.(none)|ChangeSet|20020311033237|03207 D 1.375.1.54 02/03/10 22:54:12-05:00 jejb@mulgrave.(none) +9 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Initial plug into arch split c c - still doesn't compile K 41918 P ChangeSet ------------------------------------------------ 0a0 > jejb@mulgrave.(none)|arch/i386/voyager/Makefile|20020311035244|21679|dd16c088ab1a85d4 jejb@mulgrave.(none)|arch/i386/voyager/Makefile|20020311035245|46191 > jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140213|49808|ac03dc9d49350595 jejb@mulgrave.(none)|arch/i386/voyager/voyager_basic.c|20020311035244|06363 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_cat.c|20020224140213|51425|4afbdd55fedc3919 jejb@mulgrave.(none)|arch/i386/voyager/voyager_cat.c|20020311033648|63911 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_thread.c|20020224140213|55199|411f897383390efd jejb@mulgrave.(none)|arch/i386/voyager/voyager_thread.c|20020311033648|08766 > jejb@mulgrave.(none)|arch/i386/voyager/do_timer.h|20020311035244|31812|ce936728278d42d8 jejb@mulgrave.(none)|arch/i386/voyager/do_timer.h|20020311035245|15259 > jejb@mulgrave.(none)|arch/i386/voyager/setup.c|20020311035244|35869|96097e12bd022958 jejb@mulgrave.(none)|arch/i386/voyager/setup.c|20020311035245|63158 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020311035244|10518 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311035243|45155 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/voyager/voyager_smp.c|20020311033648|03553 jejb@mulgrave.(none)|ChangeSet|20020311035412|41918 D 1.375.1.55 02/03/11 00:34:36-05:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020311052936|04758 K 2666 M jejb@mulgrave.(none)|ChangeSet|20020311052936|04758 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311053435|11466 jejb@mulgrave.(none)|ChangeSet|20020311053436|02666 D 1.375.1.56 02/03/11 01:02:59-05:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020311055930|04753 K 2667 M jejb@mulgrave.(none)|ChangeSet|20020311055930|04753 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311060258|02709 jejb@mulgrave.(none)|ChangeSet|20020311060259|02667 D 1.375.1.57 02/03/11 01:21:43-05:00 jejb@mulgrave.(none) +2 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Some setup.c modifications K 16023 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311062142|48918 > jejb@mulgrave.(none)|arch/i386/voyager/setup_arch.h|20020311062142|08270|191aa6d6ac535d24 jejb@mulgrave.(none)|arch/i386/voyager/setup_arch.h|20020311062143|17871 jejb@mulgrave.(none)|ChangeSet|20020311062143|16023 D 1.375.1.58 02/03/11 01:31:31-05:00 jejb@mulgrave.(none) +3 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Move extra export symbols to arch subdir K 29096 P ChangeSet ------------------------------------------------ 0a0 > jejb@mulgrave.(none)|arch/i386/voyager/Makefile|20020311035244|21679|dd16c088ab1a85d4 jejb@mulgrave.(none)|arch/i386/voyager/Makefile|20020311063130|48531 > jejb@mulgrave.(none)|arch/i386/voyager/i386_ksyms.c|20020311063130|54237|f2a68d32c324cda1 jejb@mulgrave.(none)|arch/i386/voyager/i386_ksyms.c|20020311063131|08561 > torvalds@athlon.transmeta.com|arch/i386/kernel/i386_ksyms.c|20020205174021|57868|87ffcb8a3a553b23 jejb@mulgrave.(none)|arch/i386/kernel/i386_ksyms.c|20020311063130|36041 jejb@mulgrave.(none)|ChangeSet|20020311063131|29096 D 1.375.1.59 02/03/11 13:44:44-05:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Voyager c c minor bug fix to remove voyager specific define K 29086 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/irq.c|20020205174021|53161|b0f85cd930bb690b jejb@mulgrave.(none)|arch/i386/kernel/irq.c|20020311184311|54418 jejb@mulgrave.(none)|ChangeSet|20020311184444|29086 D 1.375.1.60 02/03/11 13:53:01-05:00 jejb@mulgrave.(none) +4 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020311183328|17546 K 41281 M jejb@mulgrave.(none)|ChangeSet|20020311183328|17546 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311184702|50511 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311185301|46583 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311184702|26471 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020311185301|63225 jejb@mulgrave.(none)|ChangeSet|20020311185301|41281 D 1.375.1.61 02/03/11 16:30:08-05:00 jejb@mulgrave.(none) +7 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Update to get first compile with arch split K 41291 P ChangeSet ------------------------------------------------ 0a0 > jejb@mulgrave.(none)|arch/i386/voyager/Makefile|20020311035244|21679|dd16c088ab1a85d4 jejb@mulgrave.(none)|arch/i386/voyager/Makefile|20020311212805|51219 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311212805|22473 > torvalds@athlon.transmeta.com|arch/i386/Makefile|20020205174020|18710|1b8aa1f0c40a1dbf jejb@mulgrave.(none)|arch/i386/Makefile|20020311212805|09382 > jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140213|49808|ac03dc9d49350595 jejb@mulgrave.(none)|arch/i386/voyager/voyager_basic.c|20020311212805|19884 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311212805|51171 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311212805|10973 > jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c jejb@mulgrave.(none)|arch/i386/voyager/voyager_smp.c|20020311212805|02158 jejb@mulgrave.(none)|ChangeSet|20020311213008|41291 D 1.375.1.62 02/03/11 17:19:16-05:00 jejb@mulgrave.(none) +4 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge i jejb@mulgrave.(none)|ChangeSet|20020311221007|17556 K 41310 M jejb@mulgrave.(none)|ChangeSet|20020311221007|17556 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311221916|44314 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311221915|54587 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311221916|54491 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020311221554|13032 jejb@mulgrave.(none)|ChangeSet|20020311221916|41310 D 1.375.1.63 02/03/11 17:45:13-05:00 jejb@mulgrave.(none) +2 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Final changes to pull VOYAGER completely out of kernel arch directory K 41298 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311224338|58003 > jejb@mulgrave.(none)|arch/i386/voyager/do_timer.h|20020311035244|31812|ce936728278d42d8 jejb@mulgrave.(none)|arch/i386/voyager/do_timer.h|20020311224338|36531 torvalds@penguin.transmeta.com|ChangeSet|20020308015057|44839 D 1.384.1.1 02/03/11 18:47:33-05:00 jejb@mulgrave.(none) +8 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge mulgrave.(none):/home/jejb/BK/linux-2.5 c into mulgrave.(none):/home/jejb/BK/voyager-2.5 i jejb@mulgrave.(none)|ChangeSet|20020227153222|03091 i jejb@mulgrave.(none)|ChangeSet|20020227153807|03086 i jejb@mulgrave.(none)|ChangeSet|20020227154608|03079 i jejb@malley.hansenpartnership.com|ChangeSet|20020227205607|05141 i jejb@mulgrave.(none)|ChangeSet|20020311031530|23441 i jejb@mulgrave.(none)|ChangeSet|20020311033237|03207 i jejb@mulgrave.(none)|ChangeSet|20020311035412|41918 i jejb@mulgrave.(none)|ChangeSet|20020311053436|02666 i jejb@mulgrave.(none)|ChangeSet|20020311060259|02667 i jejb@mulgrave.(none)|ChangeSet|20020311062143|16023 i jejb@mulgrave.(none)|ChangeSet|20020311063131|29096 i jejb@mulgrave.(none)|ChangeSet|20020311184444|29086 i jejb@mulgrave.(none)|ChangeSet|20020311185301|41281 i jejb@mulgrave.(none)|ChangeSet|20020311213008|41291 i jejb@mulgrave.(none)|ChangeSet|20020311221916|41310 i jejb@mulgrave.(none)|ChangeSet|20020311224513|41298 K 20271 M jejb@mulgrave.(none)|ChangeSet|20020311224513|41298 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|MAINTAINERS|20020205174000|01929|3683b871be7fc6b8 jejb@mulgrave.(none)|MAINTAINERS|20020311234732|43848 > torvalds@athlon.transmeta.com|arch/i386/kernel/mpparse.c|20020205174021|05759|a518369612979315 jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020311234732|08258 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-pc.c|20020205174021|63770|524c79ffe499fd6b jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020311234732|01926 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311234732|23093 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020311234732|10129 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311234732|56833 > torvalds@athlon.transmeta.com|arch/i386/kernel/traps.c|20020205174021|43275|f01e9a814d3e2866 jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020311234732|34761 > torvalds@athlon.transmeta.com|kernel/sched.c|20020205173939|47232|5bb23172c60d3e93 jejb@mulgrave.(none)|kernel/sched.c|20020311234733|28169 jejb@mulgrave.(none)|ChangeSet|20020311231259|61287 D 1.386 02/03/11 19:17:09-05:00 jejb@mulgrave.(none) +6 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge mulgrave.(none):/home/jejb/BK/abstract-i386-2.5 c into mulgrave.(none):/home/jejb/BK/voyager-2.5 i jejb@mulgrave.(none)|ChangeSet|20020311234733|20271 K 20252 M jejb@mulgrave.(none)|ChangeSet|20020311234733|20271 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/mpparse.c|20020205174021|05759|a518369612979315 jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020312001708|08258 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-pc.c|20020205174021|63770|524c79ffe499fd6b jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020312001709|01926 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020312001709|23093 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020312001709|10129 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020312001709|56833 > torvalds@athlon.transmeta.com|arch/i386/kernel/traps.c|20020205174021|43275|f01e9a814d3e2866 jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020312001709|34761 == Documentation/voyager.txt == New file: Documentation/voyager.txt V 4 jejb@mulgrave.(none)|Documentation/voyager.txt|20020224140213|45547|2abd64f1ad30186d D 1.0 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/voyager-2.5/Documentation/voyager.txt K 45547 P Documentation/voyager.txt R 2abd64f1ad30186d X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|Documentation/voyager.txt|20020224140213|45547|2abd64f1ad30186d D 1.1 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +84 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 31612 O -rw-rw-r-- P Documentation/voyager.txt ------------------------------------------------ I0 84 Running Linux on the Voyager Architecture ========================================= \ For full details and current project status, see \ http://www.hansenpartnership.com/voyager \ The voyager architecture was designed by NCR in the mid 80s to be a fully SMP capable RAS computing architecture built around intel's 486 chip set. The voyager came in three levels of architectural sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype. The linux patches support only the Level 5 voyager architecture (any machine class 3435 and above). \ The Voyager Architecture ------------------------ \ Voyager machines consist of a Baseboard with a 386 diagnostic processor, a Power Supply Interface (PSI) a Primary and possibly Secondary Microchannel bus and between 2 and 20 voyager slots. The voyager slots can be populated with memory and cpu cards (up to 4GB memory and from 1 486 to 32 Pentium Pro processors). Internally, the voyager has a dual arbitrated system bus and a configuration and test bus (CAT). The voyager bus speed is 40MHz. Therefore (since all voyager cards are dual ported for each system bus) the maximum transfer rate is 320Mb/s but only if you have your slot configuration tuned (only memory cards can communicate with both busses at once, CPU cards utilise them one at a time). \ Voyager SMP ----------- \ Since voyager was the first intel based SMP system, it is slightly more primitive than the Intel IO-APIC approach to SMP. Voyager allows arbitrary interrupt routing (including processor affinity routing) of all 16 PC type interrupts. However it does this by using a modified 5259 master/slave chip set instead of an APIC bus. Additionally, voyager supports Cross Processor Interrupts (CPI) equivalent to the APIC IPIs. There are two routed voyager interrupt lines provided to each slot. \ Processor Cards --------------- \ These come in single, dyadic and quad configurations (the quads are problematic--see later). The maximum configuration is 8 quad cards for 32 way SMP. \ Quad Processors --------------- \ Because voyager only supplies two interrupt lines to each Processor card, the Quad processors have to be configured (and Bootstrapped) in as a pair of Master/Slave processors. \ In fact, most Quad cards only accept one VIC interrupt line, so they have one interrupt handling processor (called the VIC extended processor) and three non-interrupt handling processors. \ Current Status -------------- \ The System will boot on Mono, Dyad and Quad cards. There was originally a Quad boot problem which has been fixed by proper gdt alignment in the initial boot loader. If you still cannot get your voyager system to boot, email me at: \ \ \ The Quad cards now support using the separate Quad CPI vectors instead of going through the VIC mailbox system. \ The Level 4 architecture (3430 and 3360 Machines) seems to work, as long as you specify memory size and don't expect any of the machine specific functions (reboot, power off etc.) to work. \ A Note About Mixed CPU Systems ------------------------------ \ Linux isn't designed to handle mixed CPU systems very well. In order to get everything going you *must* make sure that your lowest capability CPU is used for booting. Also, mixing CPU classes (e.g. 486 and 586) is really not going to work very well at all. jejb@mulgrave.(none)|Documentation/voyager.txt|20020224140214|31612 D 1.2 02/02/24 08:54:23-06:00 jejb@mulgrave.(none) +14 -3 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Added note about dump and power switches K 44263 O -rw-rw-r-- P Documentation/voyager.txt ------------------------------------------------ D74 3 I76 14 The Level 4 architecture (3430 and 3360 Machines) should also work fine. \ Dump Switch ----------- \ The voyager dump switch sends out a broadcast NMI which the voyager code intercepts and does a task dump. \ Power Switch ------------ \ The front panel power switch is intercepted by the kernel and should cause a system shutdown and power off. == arch/i386/voyager/voyager_basic.c == New file: arch/i386/kernel/voyager.c V 4 jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140213|49808|ac03dc9d49350595 D 1.0 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/voyager-2.5/arch/i386/kernel/voyager.c K 49808 P arch/i386/kernel/voyager.c R ac03dc9d49350595 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140213|49808|ac03dc9d49350595 D 1.1 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +273 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 40442 O -rw-rw-r-- P arch/i386/kernel/voyager.c ------------------------------------------------ I0 273 /* Copyright (C) 1999,2001 * * Author: J.E.J.Bottomley@HansenPartnership.com * * linux/arch/i386/kernel/voyager.c * * This file contains all the voyager specific routines for getting * initialisation of the architecture to function. For additional * features see: * * voyager_cat.c - Voyager CAT bus interface * voyager_smp.c - Voyager SMP hal (emulates linux smp.c) */ \ #include #include #include #include #include #include #include #include #include #include #include #include \ #include \ int voyager_level = 0; \ struct voyager_SUS *voyager_SUS = NULL; \ void voyager_detect(struct voyager_bios_info *bios) { if(bios->len != 0xff) { int class = (bios->class_1 << 8) | (bios->class_2 & 0xff); \ printk("Voyager System detected.\n" " Class %x, Revision %d.%d\n", class, bios->major, bios->minor); if(class == VOYAGER_LEVEL4) voyager_level = 4; else if(class < VOYAGER_LEVEL5_AND_ABOVE) voyager_level = 3; else voyager_level = 5; printk(" Architecture Level %d\n", voyager_level); if(voyager_level < 4) printk("\n**WARNING**: Voyager HAL only supports Levels 4 and 5 Architectures at the moment\n\n"); } else { printk("\n\n**WARNING**: No Voyager Subsystem Found\n"); } } \ void voyager_system_interrupt(int cpl, void *dev_id, struct pt_regs *regs) { printk("Voyager: detected system interrupt\n"); } \ /* Routine to read information from the extended CMOS area */ __u8 voyager_extended_cmos_read(__u16 addr) { outb(addr & 0xff, 0x74); outb((addr >> 8) & 0xff, 0x75); return inb(0x76); } \ /* internal definitions for the SUS Click Map of memory */ \ #define CLICK_ENTRIES 16 #define CLICK_SIZE 4096 /* click to byte conversion for Length */ \ typedef struct ClickMap { struct Entry { __u32 Address; __u32 Length; } Entry[CLICK_ENTRIES]; } ClickMap_t; \ \ /* This routine is pretty much an awful hack to read the bios clickmap by * mapping it into page 0. There are usually three regions in the map: * Base Memory * Extended Memory * zero length marker for end of map * * Returns are 0 for failure and 1 for success on extracting region. */ int __init voyager_memory_detect(int region, __u32 *start, __u32 *length) { int i; int retval = 0; __u8 cmos[4]; ClickMap_t *map; unsigned long map_addr; unsigned long old; \ if(region >= CLICK_ENTRIES) { printk("Voyager: Illegal ClickMap region %d\n", region); return 0; } \ for(i = 0; i < sizeof(cmos); i++) cmos[i] = voyager_extended_cmos_read(VOYAGER_MEMORY_CLICKMAP + i); \ map_addr = *(unsigned long *)cmos; \ /* steal page 0 for this */ old = pg0[0]; pg0[0] = ((map_addr & PAGE_MASK) | _PAGE_RW | _PAGE_PRESENT); local_flush_tlb(); /* now clear everything out but page 0 */ map = (ClickMap_t *)(map_addr & (~PAGE_MASK)); \ /* zero length is the end of the clickmap */ if(map->Entry[region].Length != 0) { *length = map->Entry[region].Length * CLICK_SIZE; *start = map->Entry[region].Address; retval = 1; } \ /* replace the mapping */ pg0[0] = old; local_flush_tlb(); return retval; } \ void voyager_dump() { /* get here via a sysrq */ #ifdef CONFIG_SMP voyager_smp_dump(); #endif } \ /* voyager specific handling code for timer interrupts. Used to hand * off the timer tick to the SMP code, since the VIC doesn't have an * internal timer (The QIC does, but that's another story). */ void voyager_timer_interrupt(struct pt_regs *regs) { if((jiffies & 0x3ff) == 0) { \ /* There seems to be something flaky in either * hardware or software that is resetting the timer 0 * count to something much higher than it should be * This seems to occur in the boot sequence, just * before root is mounted. Therefore, every 10 * seconds or so, we sanity check the timer zero count * and kick it back to where it should be. * * FIXME: This is the most awful hack yet seen. I * should work out exactly what is interfering with * the timer count settings early in the boot sequence * and swiftly introduce it to something sharp and * pointy. */ __u16 val; extern spinlock_t i8253_lock; \ spin_lock(&i8253_lock); outb_p(0x00, 0x43); val = inb_p(0x40); val |= inb(0x40) << 8; spin_unlock(&i8253_lock); \ if(val > LATCH) { printk("\nVOYAGER: countdown timer value too high (%d), resetting\n\n", val); spin_lock(&i8253_lock); outb(0x34,0x43); outb_p(LATCH & 0xff , 0x40); /* LSB */ outb(LATCH >> 8 , 0x40); /* MSB */ spin_unlock(&i8253_lock); } } #ifdef CONFIG_SMP smp_vic_timer_interrupt(regs); #endif } \ void voyager_power_off(void) { printk("VOYAGER Power Off\n"); \ if(voyager_level == 5) { voyager_cat_power_off(); } else if(voyager_level == 4) { /* This doesn't apparently work on most L4 machines, * but the specs say to do this to get automatic power * off. Unfortunately, if it doesn't power off the * machine, it ends up doing a cold restart, which * isn't really intended, so comment out the code */ #if 0 int port; \ /* enable the voyager Configuration Space */ outb((inb(VOYAGER_MC_SETUP) & 0xf0) | 0x8, VOYAGER_MC_SETUP); /* the port for the power off flag is an offset from the floating base */ port = (inb(VOYAGER_SSPB_RELOCATION_PORT) << 8) + 0x21; /* set the power off flag */ outb(inb(port) | 0x1, port); #endif } /* and wait for it to happen */ for(;;) { __asm("cli"); __asm("hlt"); } } \ void voyager_restart(void) { printk("Voyager Warm Restart\n"); if(voyager_level == 5) { /* write magic values to the RTC to inform system that * shutdown is beginning */ outb(0x8f, 0x70); outb(0x5 , 0x71); udelay(50); outb(0xfe,0x64); /* pull reset low */ } else if(voyager_level == 4) { __u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT)<<8; __u8 basebd = inb(VOYAGER_MC_SETUP); outb(basebd | 0x08, VOYAGER_MC_SETUP); outb(0x02, catbase + 0x21); } for(;;) { asm("cli"); asm("hlt"); } } \ void voyager_handle_nmi(void) { __u8 dumpval __attribute__((unused)) = inb(0xf823); __u8 swnmi __attribute__((unused)) = inb(0xf813); extern void show_stack(unsigned long *); \ /* FIXME: assume dump switch pressed */ /* check to see if the dump switch was pressed */ VDEBUG(("VOYAGER: dumpval = 0x%x, swnmi = 0x%x\n", dumpval, swnmi)); /* clear swnmi */ outb(0xff, 0xf813); /* tell SUS to ignore dump */ if(voyager_level == 5 && voyager_SUS != NULL) { if(voyager_SUS->SUS_mbox == VOYAGER_DUMP_BUTTON_NMI) { voyager_SUS->kernel_mbox = VOYAGER_NO_COMMAND; voyager_SUS->kernel_flags |= VOYAGER_OS_IN_PROGRESS; udelay(1000); voyager_SUS->kernel_mbox = VOYAGER_IGNORE_DUMP; voyager_SUS->kernel_flags &= ~VOYAGER_OS_IN_PROGRESS; } } printk(KERN_ERR "VOYAGER: Dump switch pressed, printing CPU%d tracebacks\n", smp_processor_id()); show_stack(NULL); show_state(); } jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224140214|40442 D 1.2 02/02/24 08:54:23-06:00 jejb@mulgrave.(none) +28 -4 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add the restart and halt functions K 4496 O -rw-rw-r-- P arch/i386/kernel/voyager.c ------------------------------------------------ I22 1 #include D27 1 I27 1 #include D53 2 I54 3 /* install the power off handler */ pm_power_off = voyager_power_off; } else { I222 11 /* copied from process.c */ static inline void kb_wait(void) { int i; \ for (i=0; i<0x10000; i++) if ((inb_p(0x64) & 0x02) == 0) break; } \ D224 1 I224 1 machine_restart(char *cmd) I226 2 kb_wait(); \ I272 9 } \ \ \ void machine_halt(void) { /* treat a halt like a power off */ machine_power_off(); jejb@mulgrave.(none)|arch/i386/kernel/voyager.c|20020224145423|04496 D 1.3 02/03/10 22:36:48-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Rename: arch/i386/kernel/voyager.c -> arch/i386/voyager/voyager.c K 58331 O -rw-rw-r-- P arch/i386/voyager/voyager.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/voyager/voyager.c|20020311033648|58331 D 1.4 02/03/10 22:38:31-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Rename: arch/i386/voyager/voyager.c -> arch/i386/voyager/voyager_basic.c K 35633 O -rw-rw-r-- P arch/i386/voyager/voyager_basic.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/voyager/voyager_basic.c|20020311033831|35633 D 1.5 02/03/10 22:52:44-05:00 jejb@mulgrave.(none) +2 -1 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c A K 6363 O -rw-rw-r-- P arch/i386/voyager/voyager_basic.c ------------------------------------------------ I29 1 #include D264 1 I264 1 mca_nmi_hook(void) jejb@mulgrave.(none)|arch/i386/voyager/voyager_basic.c|20020311035244|06363 D 1.6 02/03/11 16:28:05-05:00 jejb@mulgrave.(none) +13 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add more power/reboot functions K 19884 O -rw-rw-r-- P arch/i386/voyager/voyager_basic.c ------------------------------------------------ I31 7 /* * Power off function, if any */ void (*pm_power_off)(void); \ int reboot_thru_bios; \ I297 6 } \ void machine_power_off(void) { if (pm_power_off) pm_power_off(); == arch/i386/voyager/voyager_cat.c == New file: arch/i386/kernel/voyager_cat.c V 4 jejb@mulgrave.(none)|arch/i386/kernel/voyager_cat.c|20020224140213|51425|4afbdd55fedc3919 D 1.0 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/voyager-2.5/arch/i386/kernel/voyager_cat.c K 51425 P arch/i386/kernel/voyager_cat.c R 4afbdd55fedc3919 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/kernel/voyager_cat.c|20020224140213|51425|4afbdd55fedc3919 D 1.1 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +1179 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 52200 O -rw-rw-r-- P arch/i386/kernel/voyager_cat.c ------------------------------------------------ I0 1179 /* -*- mode: c; c-basic-offset: 8 -*- */ \ /* Copyright (C) 1999,2001 * * Author: J.E.J.Bottomley@HansenPartnership.com * * linux/arch/i386/kernel/voyager_cat.c * * This file contains all the logic for manipulating the CAT bus * in a level 5 machine. * * The CAT bus is a serial configuration and test bus. Its primary * uses are to probe the initial configuration of the system and to * diagnose error conditions when a system interrupt occurs. The low * level interface is fairly primitive, so most of this file consists * of bit shift manipulations to send and receive packets on the * serial bus */ \ #include #include #include #include #include #include #include #include #include #include #include #include \ #ifdef VOYAGER_CAT_DEBUG #define CDEBUG(x) printk x #else #define CDEBUG(x) #endif \ /* the CAT command port */ #define CAT_CMD (sspb + 0xe) /* the CAT data port */ #define CAT_DATA (sspb + 0xd) \ /* the internal cat functions */ static void cat_pack(__u8 *msg, __u16 start_bit, __u8 *data, __u16 num_bits); static void cat_unpack(__u8 *msg, __u16 start_bit, __u8 *data, __u16 num_bits); static void cat_build_header(__u8 *header, const __u16 len, const __u16 smallest_reg_bits, const __u16 longest_reg_bits); static int cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 op); static int cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 *value); static int cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, __u8 pad_bits); static int cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 value); static int cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 *value); static int cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset, __u16 len, void *buf); static int cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 value); static int cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp); static int cat_connect(voyager_module_t *modp, voyager_asic_t *asicp); \ static inline const char * cat_module_name(int module_id) { switch(module_id) { case 0x10: return "Processor Slot 0"; case 0x11: return "Processor Slot 1"; case 0x12: return "Processor Slot 2"; case 0x13: return "Processor Slot 4"; case 0x14: return "Memory Slot 0"; case 0x15: return "Memory Slot 1"; case 0x18: return "Primary Microchannel"; case 0x19: return "Secondary Microchannel"; case 0x1a: return "Power Supply Interface"; case 0x1c: return "Processor Slot 5"; case 0x1d: return "Processor Slot 6"; case 0x1e: return "Processor Slot 7"; case 0x1f: return "Processor Slot 8"; default: return "Unknown Module"; } } \ static int sspb = 0; /* stores the super port location */ int voyager_8slot = 0; /* set to true if a 51xx monster */ \ voyager_module_t *voyager_cat_list; \ /* the I/O port assignments for the VIC and QIC */ static struct resource vic_res = { "Voyager Interrupt Controller", 0xFC00, 0xFC6F }; static struct resource qic_res = { "Quad Interrupt Controller", 0xFC70, 0xFCFF }; \ /* This function is used to pack a data bit stream inside a message. * It writes num_bits of the data buffer in msg starting at start_bit. * Note: This function assumes that any unused bit in the data stream * is set to zero so that the ors will work correctly */ #define BITS_PER_BYTE 8 static void cat_pack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits) { /* compute initial shift needed */ const __u16 offset = start_bit % BITS_PER_BYTE; __u16 len = num_bits / BITS_PER_BYTE; __u16 byte = start_bit / BITS_PER_BYTE; __u16 residue = (num_bits % BITS_PER_BYTE) + offset; int i; \ /* adjust if we have more than a byte of residue */ if(residue >= BITS_PER_BYTE) { residue -= BITS_PER_BYTE; len++; } \ /* clear out the bits. We assume here that if len==0 then * residue >= offset. This is always true for the catbus * operations */ msg[byte] &= 0xff << (BITS_PER_BYTE - offset); msg[byte++] |= data[0] >> offset; if(len == 0) return; for(i = 1; i < len; i++) msg[byte++] = (data[i-1] << (BITS_PER_BYTE - offset)) | (data[i] >> offset); if(residue != 0) { __u8 mask = 0xff >> residue; __u8 last_byte = data[i-1] << (BITS_PER_BYTE - offset) | (data[i] >> offset); last_byte &= ~mask; msg[byte] &= mask; msg[byte] |= last_byte; } return; } /* unpack the data again (same arguments as cat_pack()). data buffer * must be zero populated. * * Function: given a message string move to start_bit and copy num_bits into * data (starting at bit 0 in data). */ static void cat_unpack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits) { /* compute initial shift needed */ const __u16 offset = start_bit % BITS_PER_BYTE; __u16 len = num_bits / BITS_PER_BYTE; const __u8 last_bits = num_bits % BITS_PER_BYTE; __u16 byte = start_bit / BITS_PER_BYTE; int i; \ if(last_bits != 0) len++; \ /* special case: want < 8 bits from msg and we can get it from * a single byte of the msg */ if(len == 0 && BITS_PER_BYTE - offset >= num_bits) { data[0] = msg[byte] << offset; data[0] &= 0xff >> (BITS_PER_BYTE - num_bits); return; } for(i = 0; i < len; i++) { /* this annoying if has to be done just in case a read of * msg one beyond the array causes a panic */ if(offset != 0) { data[i] = msg[byte++] << offset; data[i] |= msg[byte] >> (BITS_PER_BYTE - offset); } else { data[i] = msg[byte++]; } } /* do we need to truncate the final byte */ if(last_bits != 0) { data[i-1] &= 0xff << (BITS_PER_BYTE - last_bits); } return; } \ static void cat_build_header(__u8 *header, const __u16 len, const __u16 smallest_reg_bits, const __u16 longest_reg_bits) { int i; __u16 start_bit = (smallest_reg_bits - 1) % BITS_PER_BYTE; __u8 *last_byte = &header[len - 1]; \ if(start_bit == 0) start_bit = 1; /* must have at least one bit in the hdr */ for(i=0; i < len; i++) header[i] = 0; \ for(i = start_bit; i > 0; i--) *last_byte = ((*last_byte) << 1) + 1; \ } \ static int cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 op) { __u8 parity, inst, inst_buf[4] = { 0 }; __u8 iseq[VOYAGER_MAX_SCAN_PATH], hseq[VOYAGER_MAX_REG_SIZE]; __u16 ibytes, hbytes, padbits; int i; /* * Parity is the parity of the register number + 1 (READ_REGISTER * and WRITE_REGISTER always add '1' to the number of bits == 1) */ parity = (__u8)(1 + (reg & 0x01) + ((__u8)(reg & 0x02) >> 1) + ((__u8)(reg & 0x04) >> 2) + ((__u8)(reg & 0x08) >> 3)) % 2; \ inst = ((parity << 7) | (reg << 2) | op); \ outb(VOYAGER_CAT_IRCYC, CAT_CMD); if(!modp->scan_path_connected) { if(asicp->asic_id != VOYAGER_CAT_ID) { printk("**WARNING***: cat_sendinst has disconnected scan path not to CAT asic\n"); return 1; } outb(VOYAGER_CAT_HEADER, CAT_DATA); outb(inst, CAT_DATA); if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) { CDEBUG(("VOYAGER CAT: cat_sendinst failed to get CAT_HEADER\n")); return 1; } return 0; } ibytes = modp->inst_bits / BITS_PER_BYTE; if((padbits = modp->inst_bits % BITS_PER_BYTE) != 0) { padbits = BITS_PER_BYTE - padbits; ibytes++; } hbytes = modp->largest_reg / BITS_PER_BYTE; if(modp->largest_reg % BITS_PER_BYTE) hbytes++; CDEBUG(("cat_sendinst: ibytes=%d, hbytes=%d\n", ibytes, hbytes)); /* initialise the instruction sequence to 0xff */ for(i=0; i < ibytes + hbytes; i++) iseq[i] = 0xff; cat_build_header(hseq, hbytes, modp->smallest_reg, modp->largest_reg); cat_pack(iseq, modp->inst_bits, hseq, hbytes * BITS_PER_BYTE); inst_buf[0] = inst; inst_buf[1] = 0xFF >> (modp->largest_reg % BITS_PER_BYTE); cat_pack(iseq, asicp->bit_location, inst_buf, asicp->ireg_length); #ifdef VOYAGER_CAT_DEBUG printk("ins = 0x%x, iseq: ", inst); for(i=0; i< ibytes + hbytes; i++) printk("0x%x ", iseq[i]); printk("\n"); #endif if(cat_shiftout(iseq, ibytes, hbytes, padbits)) { CDEBUG(("VOYAGER CAT: cat_sendinst: cat_shiftout failed\n")); return 1; } CDEBUG(("CAT SHIFTOUT DONE\n")); return 0; } \ static int cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 *value) { if(!modp->scan_path_connected) { if(asicp->asic_id != VOYAGER_CAT_ID) { CDEBUG(("VOYAGER CAT: ERROR: cat_getdata to CAT asic with scan path connected\n")); return 1; } if(reg > VOYAGER_SUBADDRHI) outb(VOYAGER_CAT_RUN, CAT_CMD); outb(VOYAGER_CAT_DRCYC, CAT_CMD); outb(VOYAGER_CAT_HEADER, CAT_DATA); *value = inb(CAT_DATA); outb(0xAA, CAT_DATA); if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) { CDEBUG(("cat_getdata: failed to get VOYAGER_CAT_HEADER\n")); return 1; } return 0; } else { __u16 sbits = modp->num_asics -1 + asicp->ireg_length; __u16 sbytes = sbits / BITS_PER_BYTE; __u16 tbytes; __u8 string[VOYAGER_MAX_SCAN_PATH], trailer[VOYAGER_MAX_REG_SIZE]; __u8 padbits; int i; outb(VOYAGER_CAT_DRCYC, CAT_CMD); \ if((padbits = sbits % BITS_PER_BYTE) != 0) { padbits = BITS_PER_BYTE - padbits; sbytes++; } tbytes = asicp->ireg_length / BITS_PER_BYTE; if(asicp->ireg_length % BITS_PER_BYTE) tbytes++; CDEBUG(("cat_getdata: tbytes = %d, sbytes = %d, padbits = %d\n", tbytes, sbytes, padbits)); cat_build_header(trailer, tbytes, 1, asicp->ireg_length); \ for(i = tbytes - 1; i >= 0; i--) { outb(trailer[i], CAT_DATA); string[sbytes + i] = inb(CAT_DATA); } \ for(i = sbytes - 1; i >= 0; i--) { outb(0xaa, CAT_DATA); string[i] = inb(CAT_DATA); } *value = 0; cat_unpack(string, padbits + (tbytes * BITS_PER_BYTE) + asicp->asic_location, value, asicp->ireg_length); #ifdef VOYAGER_CAT_DEBUG printk("value=0x%x, string: ", *value); for(i=0; i< tbytes+sbytes; i++) printk("0x%x ", string[i]); printk("\n"); #endif /* sanity check the rest of the return */ for(i=0; i < tbytes; i++) { __u8 input = 0; \ cat_unpack(string, padbits + (i * BITS_PER_BYTE), &input, BITS_PER_BYTE); if(trailer[i] != input) { CDEBUG(("cat_getdata: failed to sanity check rest of ret(%d) 0x%x != 0x%x\n", i, input, trailer[i])); return 1; } } CDEBUG(("cat_getdata DONE\n")); return 0; } } \ static int cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, __u8 pad_bits) { int i; for(i = data_bytes + header_bytes - 1; i >= header_bytes; i--) outb(data[i], CAT_DATA); \ for(i = header_bytes - 1; i >= 0; i--) { __u8 header = 0; __u8 input; \ outb(data[i], CAT_DATA); input = inb(CAT_DATA); CDEBUG(("cat_shiftout: returned 0x%x\n", input)); cat_unpack(data, ((data_bytes + i) * BITS_PER_BYTE) - pad_bits, &header, BITS_PER_BYTE); if(input != header) { CDEBUG(("VOYAGER CAT: cat_shiftout failed to return header 0x%x != 0x%x\n", input, header)); return 1; } } return 0; } \ static int cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 value) { outb(VOYAGER_CAT_DRCYC, CAT_CMD); if(!modp->scan_path_connected) { if(asicp->asic_id != VOYAGER_CAT_ID) { CDEBUG(("VOYAGER CAT: ERROR: scan path disconnected when asic != CAT\n")); return 1; } outb(VOYAGER_CAT_HEADER, CAT_DATA); outb(value, CAT_DATA); if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) { CDEBUG(("cat_senddata: failed to get correct header response to sent data\n")); return 1; } if(reg > VOYAGER_SUBADDRHI) { outb(VOYAGER_CAT_RUN, CAT_CMD); outb(VOYAGER_CAT_END, CAT_CMD); outb(VOYAGER_CAT_RUN, CAT_CMD); } return 0; } else { __u16 hbytes = asicp->ireg_length / BITS_PER_BYTE; __u16 dbytes = (modp->num_asics - 1 + asicp->ireg_length)/BITS_PER_BYTE; __u8 padbits, dseq[VOYAGER_MAX_SCAN_PATH], hseq[VOYAGER_MAX_REG_SIZE]; int i; \ if((padbits = (modp->num_asics - 1 + asicp->ireg_length) % BITS_PER_BYTE) != 0) { padbits = BITS_PER_BYTE - padbits; dbytes++; } if(asicp->ireg_length % BITS_PER_BYTE) hbytes++; cat_build_header(hseq, hbytes, 1, asicp->ireg_length); for(i = 0; i < dbytes + hbytes; i++) dseq[i] = 0xff; CDEBUG(("cat_senddata: dbytes=%d, hbytes=%d, padbits=%d\n", dbytes, hbytes, padbits)); cat_pack(dseq, modp->num_asics - 1 + asicp->ireg_length, hseq, hbytes * BITS_PER_BYTE); cat_pack(dseq, asicp->asic_location, &value, asicp->ireg_length); #ifdef VOYAGER_CAT_DEBUG printk("dseq "); for(i=0; i 1) { /* set auto increment */ __u8 newval; if(cat_read(modp, asicp, VOYAGER_AUTO_INC_REG, &val)) { CDEBUG(("cat_subaddrsetup: read of VOYAGER_AUTO_INC_REG failed\n")); return 1; } CDEBUG(("cat_subaddrsetup: VOYAGER_AUTO_INC_REG = 0x%x\n", val)); newval = val | VOYAGER_AUTO_INC; if(newval != val) { if(cat_write(modp, asicp, VOYAGER_AUTO_INC_REG, val)) { CDEBUG(("cat_subaddrsetup: write to VOYAGER_AUTO_INC_REG failed\n")); return 1; } } } if(cat_write(modp, asicp, VOYAGER_SUBADDRLO, (__u8)(offset &0xff))) { CDEBUG(("cat_subaddrsetup: write to SUBADDRLO failed\n")); return 1; } if(asicp->subaddr > VOYAGER_SUBADDR_LO) { if(cat_write(modp, asicp, VOYAGER_SUBADDRHI, (__u8)(offset >> 8))) { CDEBUG(("cat_subaddrsetup: write to SUBADDRHI failed\n")); return 1; } cat_read(modp, asicp, VOYAGER_SUBADDRHI, &val); CDEBUG(("cat_subaddrsetup: offset = %d, hi = %d\n", offset, val)); } cat_read(modp, asicp, VOYAGER_SUBADDRLO, &val); CDEBUG(("cat_subaddrsetup: offset = %d, lo = %d\n", offset, val)); return 0; } static int cat_subwrite(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset, __u16 len, void *buf) { int i, retval; \ /* FIXME: need special actions for VOYAGER_CAT_ID here */ if(asicp->asic_id == VOYAGER_CAT_ID) { CDEBUG(("cat_subwrite: ATTEMPT TO WRITE TO CAT ASIC\n")); /* FIXME -- This is supposed to be handled better * There is a problem writing to the cat asic in the * PSI. The 30us delay seems to work, though */ udelay(30); } if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) { printk("cat_subwrite: cat_subaddrsetup FAILED\n"); return retval; } if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_WRITE_CONFIG)) { printk("cat_subwrite: cat_sendinst FAILED\n"); return 1; } for(i = 0; i < len; i++) { if(cat_senddata(modp, asicp, 0xFF, ((__u8 *)buf)[i])) { printk("cat_subwrite: cat_sendata element at %d FAILED\n", i); return 1; } } return 0; } static int cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset, __u16 len, void *buf) { int i, retval; \ if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) { CDEBUG(("cat_subread: cat_subaddrsetup FAILED\n")); return retval; } \ if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_READ_CONFIG)) { CDEBUG(("cat_subread: cat_sendinst failed\n")); return 1; } for(i = 0; i < len; i++) { if(cat_getdata(modp, asicp, 0xFF, &((__u8 *)buf)[i])) { CDEBUG(("cat_subread: cat_getdata element %d failed\n", i)); return 1; } } return 0; } \ \ /* buffer for storing EPROM data read in during initialisation */ static __initdata __u8 eprom_buf[0xFFFF]; static voyager_module_t *voyager_initial_module; \ /* Initialise the cat bus components. We assume this is called by the * boot cpu *after* all memory initialisation has been done (so we can * use kmalloc) but before smp initialisation, so we can probe the SMP * configuration and pick up necessary information. */ void voyager_cat_init(void) { voyager_module_t **modpp = &voyager_initial_module; voyager_asic_t **asicpp; voyager_asic_t *qabc_asic = NULL; int i, j; unsigned long qic_addr = 0; __u8 qabc_data[0x20]; __u8 num_submodules, val; voyager_eprom_hdr_t *eprom_hdr = (voyager_eprom_hdr_t *)&eprom_buf[0]; __u8 cmos[4]; unsigned long addr; /* initiallise the SUS mailbox */ for(i=0; iSUS_version); voyager_SUS->kernel_version = VOYAGER_MAILBOX_VERSION; voyager_SUS->kernel_flags = VOYAGER_OS_HAS_SYSINT; } \ /* clear the processor counts */ voyager_extended_vic_processors = 0; voyager_quad_processors = 0; \ \ \ printk("VOYAGER: beginning CAT bus probe\n"); /* set up the SuperSet Port Block which tells us where the * CAT communication port is */ sspb = inb(VOYAGER_SSPB_RELOCATION_PORT) * 0x100; VDEBUG(("VOYAGER DEBUG: sspb = 0x%x\n", sspb)); \ /* now find out if were 8 slot or normal */ if((inb(VIC_PROC_WHO_AM_I) & EIGHT_SLOT_IDENTIFIER) == EIGHT_SLOT_IDENTIFIER) { voyager_8slot = 1; printk(KERN_NOTICE "Voyager: Eight slot 51xx configuration detected\n"); } \ for(i = VOYAGER_MIN_MODULE; i <= VOYAGER_MAX_MODULE; i++) { __u8 input; int asic; __u16 eprom_size; __u16 sp_offset; \ outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT); outb(i, VOYAGER_CAT_CONFIG_PORT); \ /* check the presence of the module */ outb(VOYAGER_CAT_RUN, CAT_CMD); outb(VOYAGER_CAT_IRCYC, CAT_CMD); outb(VOYAGER_CAT_HEADER, CAT_DATA); /* stream series of alternating 1's and 0's to stimulate * response */ outb(0xAA, CAT_DATA); input = inb(CAT_DATA); outb(VOYAGER_CAT_END, CAT_CMD); if(input != VOYAGER_CAT_HEADER) { continue; } CDEBUG(("VOYAGER DEBUG: found module id 0x%x, %s\n", i, cat_module_name(i))); *modpp = kmalloc(sizeof(voyager_module_t), GFP_KERNEL); /*&voyager_module_storage[cat_count++];*/ if(*modpp == NULL) { printk("**WARNING** kmalloc failure in cat_init\n"); continue; } memset(*modpp, 0, sizeof(voyager_module_t)); /* need temporary asic for cat_subread. It will be * filled in correctly later */ (*modpp)->asic = kmalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count];*/ if((*modpp)->asic == NULL) { printk("**WARNING** kmalloc failure in cat_init\n"); continue; } memset((*modpp)->asic, 0, sizeof(voyager_asic_t)); (*modpp)->asic->asic_id = VOYAGER_CAT_ID; (*modpp)->asic->subaddr = VOYAGER_SUBADDR_HI; (*modpp)->module_addr = i; (*modpp)->scan_path_connected = 0; if(i == VOYAGER_PSI) { /* Exception leg for modules with no EEPROM */ printk("Module \"%s\"\n", cat_module_name(i)); continue; } CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET)); outb(VOYAGER_CAT_RUN, CAT_CMD); cat_disconnect(*modpp, (*modpp)->asic); if(cat_subread(*modpp, (*modpp)->asic, VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size), &eprom_size)) { printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i); outb(VOYAGER_CAT_END, CAT_CMD); continue; } if(eprom_size > sizeof(eprom_buf)) { printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size); outb(VOYAGER_CAT_END, CAT_CMD); continue; } outb(VOYAGER_CAT_END, CAT_CMD); outb(VOYAGER_CAT_RUN, CAT_CMD); CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size)); if(cat_subread(*modpp, (*modpp)->asic, 0, eprom_size, eprom_buf)) { outb(VOYAGER_CAT_END, CAT_CMD); continue; } outb(VOYAGER_CAT_END, CAT_CMD); printk("Module \"%s\", version 0x%x, tracer 0x%x, asics %d\n", cat_module_name(i), eprom_hdr->version_id, *((__u32 *)eprom_hdr->tracer), eprom_hdr->num_asics); (*modpp)->ee_size = eprom_hdr->ee_size; (*modpp)->num_asics = eprom_hdr->num_asics; asicpp = &((*modpp)->asic); sp_offset = eprom_hdr->scan_path_offset; /* All we really care about are the Quad cards. We * identify them because they are in a processor slot * and have only four asics */ if((i < 0x10 || (i>=0x14 && i < 0x1c) || i>0x1f)) { modpp = &((*modpp)->next); continue; } /* Now we know it's in a processor slot, does it have * a quad baseboard submodule */ outb(VOYAGER_CAT_RUN, CAT_CMD); cat_read(*modpp, (*modpp)->asic, VOYAGER_SUBMODPRESENT, &num_submodules); /* lowest two bits, active low */ num_submodules = ~(0xfc | num_submodules); CDEBUG(("VOYAGER CAT: %d submodules present\n", num_submodules)); if(num_submodules == 0) { /* fill in the dyadic extended processors */ __u8 cpu = i & 0x07; \ printk("Module \"%s\": Dyadic Processor Card\n", cat_module_name(i)); voyager_extended_vic_processors |= (1<asic, VOYAGER_SUBMODSELECT, &val); CDEBUG(("cat_init: SUBMODSELECT value = 0x%x\n", val)); val = (val & 0x7c) | VOYAGER_QUAD_BASEBOARD; cat_write(*modpp, (*modpp)->asic, VOYAGER_SUBMODSELECT, val); \ outb(VOYAGER_CAT_END, CAT_CMD); \ CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET)); outb(VOYAGER_CAT_RUN, CAT_CMD); cat_disconnect(*modpp, (*modpp)->asic); if(cat_subread(*modpp, (*modpp)->asic, VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size), &eprom_size)) { printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i); outb(VOYAGER_CAT_END, CAT_CMD); continue; } if(eprom_size > sizeof(eprom_buf)) { printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size); outb(VOYAGER_CAT_END, CAT_CMD); continue; } outb(VOYAGER_CAT_END, CAT_CMD); outb(VOYAGER_CAT_RUN, CAT_CMD); CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size)); if(cat_subread(*modpp, (*modpp)->asic, 0, eprom_size, eprom_buf)) { outb(VOYAGER_CAT_END, CAT_CMD); continue; } outb(VOYAGER_CAT_END, CAT_CMD); /* Now do everything for the QBB submodule 1 */ (*modpp)->ee_size = eprom_hdr->ee_size; (*modpp)->num_asics = eprom_hdr->num_asics; asicpp = &((*modpp)->asic); sp_offset = eprom_hdr->scan_path_offset; /* get rid of the dummy CAT asic and read the real one */ kfree((*modpp)->asic); for(asic=0; asic < (*modpp)->num_asics; asic++) { int j; voyager_asic_t *asicp = *asicpp = kmalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count++];*/ voyager_sp_table_t *sp_table; voyager_at_t *asic_table; voyager_jtt_t *jtag_table; \ if(asicp == NULL) { printk("**WARNING** kmalloc failure in cat_init\n"); continue; } memset(asicp, 0, sizeof(voyager_asic_t)); asicpp = &(asicp->next); asicp->asic_location = asic; sp_table = (voyager_sp_table_t *)(eprom_buf + sp_offset); asicp->asic_id = sp_table->asic_id; asic_table = (voyager_at_t *)(eprom_buf + sp_table->asic_data_offset); for(j=0; j<4; j++) asicp->jtag_id[j] = asic_table->jtag_id[j]; jtag_table = (voyager_jtt_t *)(eprom_buf + asic_table->jtag_offset); asicp->ireg_length = jtag_table->ireg_len; asicp->bit_location = (*modpp)->inst_bits; (*modpp)->inst_bits += asicp->ireg_length; if(asicp->ireg_length > (*modpp)->largest_reg) (*modpp)->largest_reg = asicp->ireg_length; if (asicp->ireg_length < (*modpp)->smallest_reg || (*modpp)->smallest_reg == 0) (*modpp)->smallest_reg = asicp->ireg_length; CDEBUG(("asic 0x%x, ireg_length=%d, bit_location=%d\n", asicp->asic_id, asicp->ireg_length, asicp->bit_location)); if(asicp->asic_id == VOYAGER_QUAD_QABC) { CDEBUG(("VOYAGER CAT: QABC ASIC found\n")); qabc_asic = asicp; } sp_offset += sizeof(voyager_sp_table_t); } CDEBUG(("Module inst_bits = %d, largest_reg = %d, smallest_reg=%d\n", (*modpp)->inst_bits, (*modpp)->largest_reg, (*modpp)->smallest_reg)); /* OK, now we have the QUAD ASICs set up, use them. * we need to: * * 1. Find the Memory area for the Quad CPIs. * 2. Find the Extended VIC processor * 3. Configure a second extended VIC processor (This * cannot be done for the 51xx. * */ outb(VOYAGER_CAT_RUN, CAT_CMD); cat_connect(*modpp, (*modpp)->asic); CDEBUG(("CAT CONNECTED!!\n")); cat_subread(*modpp, qabc_asic, 0, sizeof(qabc_data), qabc_data); qic_addr = qabc_data[5] << 8; qic_addr = (qic_addr | qabc_data[6]) << 8; qic_addr = (qic_addr | qabc_data[7]) << 8; printk("Module \"%s\": Quad Processor Card; CPI 0x%lx, SET=0x%x\n", cat_module_name(i), qic_addr, qabc_data[8]); #if 0 /* plumbing fails---FIXME */ if((qabc_data[8] & 0xf0) == 0) { /* FIXME: 32 way 8 CPU slot monster cannot be * plumbed this way---need to check for it */ \ printk("Plumbing second Extended Quad Processor\n"); /* second VIC line hardwired to Quad CPU 1 */ qabc_data[8] |= 0x20; cat_subwrite(*modpp, qabc_asic, 8, 1, &qabc_data[8]); #ifdef VOYAGER_CAT_DEBUG /* verify plumbing */ cat_subread(*modpp, qabc_asic, 8, 1, &qabc_data[8]); if((qabc_data[8] & 0xf0) == 0) { CDEBUG(("PLUMBING FAILED: 0x%x\n", qabc_data[8])); } #endif } #endif \ { struct resource *res = kmalloc(sizeof(struct resource),GFP_KERNEL); memset(res, 0, sizeof(struct resource)); res->name = kmalloc(128, GFP_KERNEL); sprintf((char *)res->name, "Voyager %s Quad CPI", cat_module_name(i)); res->start = qic_addr; res->end = qic_addr + 0x3ff; request_resource(&iomem_resource, res); } \ qic_addr = (unsigned long)ioremap(qic_addr, 0x400); for(j = 0; j < 4; j++) { __u8 cpu; \ if(voyager_8slot) { /* 8 slot has a different mapping, * each slot has only one vic line, so * 1 cpu in each slot must be < 8 */ cpu = (i & 0x07) + j*8; } else { cpu = (i & 0x03) + j*4; } if( (qabc_data[8] & (1<next); } *modpp = NULL; printk("CAT Bus Initialisation finished: extended procs 0x%x, quad procs 0x%x, allowed vic boot = 0x%x\n", voyager_extended_vic_processors, voyager_quad_processors, voyager_allowed_boot_processors); request_resource(&ioport_resource, &vic_res); if(voyager_quad_processors) request_resource(&ioport_resource, &qic_res); /* set up the front power switch */ } \ int voyager_cat_readb(__u8 module, __u8 asic, int reg) { return 0; } \ static int cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp) { __u8 val; int err = 0; \ if(!modp->scan_path_connected) return 0; if(asicp->asic_id != VOYAGER_CAT_ID) { CDEBUG(("cat_disconnect: ASIC is not CAT\n")); return 1; } err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val); if(err) { CDEBUG(("cat_disconnect: failed to read SCANPATH\n")); return err; } val &= VOYAGER_DISCONNECT_ASIC; err = cat_write(modp, asicp, VOYAGER_SCANPATH, val); if(err) { CDEBUG(("cat_disconnect: failed to write SCANPATH\n")); return err; } outb(VOYAGER_CAT_END, CAT_CMD); outb(VOYAGER_CAT_RUN, CAT_CMD); modp->scan_path_connected = 0; \ return 0; } \ static int cat_connect(voyager_module_t *modp, voyager_asic_t *asicp) { __u8 val; int err = 0; \ if(modp->scan_path_connected) return 0; if(asicp->asic_id != VOYAGER_CAT_ID) { CDEBUG(("cat_connect: ASIC is not CAT\n")); return 1; } \ err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val); if(err) { CDEBUG(("cat_connect: failed to read SCANPATH\n")); return err; } val |= VOYAGER_CONNECT_ASIC; err = cat_write(modp, asicp, VOYAGER_SCANPATH, val); if(err) { CDEBUG(("cat_connect: failed to write SCANPATH\n")); return err; } outb(VOYAGER_CAT_END, CAT_CMD); outb(VOYAGER_CAT_RUN, CAT_CMD); modp->scan_path_connected = 1; \ return 0; } \ void voyager_cat_power_off(void) { /* Power the machine off by writing to the PSI over the CAT * bus */ __u8 data; voyager_module_t psi = { 0 }; voyager_asic_t psi_asic = { 0 }; \ psi.asic = &psi_asic; psi.asic->asic_id = VOYAGER_CAT_ID; psi.asic->subaddr = VOYAGER_SUBADDR_HI; psi.module_addr = VOYAGER_PSI; psi.scan_path_connected = 0; \ outb(VOYAGER_CAT_END, CAT_CMD); /* Connect the PSI to the CAT Bus */ outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT); outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT); outb(VOYAGER_CAT_RUN, CAT_CMD); cat_disconnect(&psi, &psi_asic); /* Read the status */ cat_subread(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data); outb(VOYAGER_CAT_END, CAT_CMD); CDEBUG(("PSI STATUS 0x%x\n", data)); /* These two writes are power off prep and perform */ data = PSI_CLEAR; outb(VOYAGER_CAT_RUN, CAT_CMD); cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data); outb(VOYAGER_CAT_END, CAT_CMD); data = PSI_POWER_DOWN; outb(VOYAGER_CAT_RUN, CAT_CMD); cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data); outb(VOYAGER_CAT_END, CAT_CMD); } \ struct voyager_status voyager_status = { 0 }; \ void voyager_cat_psi(__u8 cmd, __u16 reg, __u8 *data) { voyager_module_t psi = { 0 }; voyager_asic_t psi_asic = { 0 }; \ psi.asic = &psi_asic; psi.asic->asic_id = VOYAGER_CAT_ID; psi.asic->subaddr = VOYAGER_SUBADDR_HI; psi.module_addr = VOYAGER_PSI; psi.scan_path_connected = 0; \ outb(VOYAGER_CAT_END, CAT_CMD); /* Connect the PSI to the CAT Bus */ outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT); outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT); outb(VOYAGER_CAT_RUN, CAT_CMD); cat_disconnect(&psi, &psi_asic); switch(cmd) { case VOYAGER_PSI_READ: cat_read(&psi, &psi_asic, reg, data); break; case VOYAGER_PSI_WRITE: cat_write(&psi, &psi_asic, reg, *data); break; case VOYAGER_PSI_SUBREAD: cat_subread(&psi, &psi_asic, reg, 1, data); break; case VOYAGER_PSI_SUBWRITE: cat_subwrite(&psi, &psi_asic, reg, 1, data); break; default: printk(KERN_ERR "Voyager PSI, unrecognised command %d\n", cmd); break; } outb(VOYAGER_CAT_END, CAT_CMD); } \ void voyager_cat_do_common_interrupt(void) { /* This is caused either by a memory parity error or something * in the PSI */ __u8 data; voyager_module_t psi = { 0 }; voyager_asic_t psi_asic = { 0 }; struct voyager_psi psi_reg; int i; re_read: psi.asic = &psi_asic; psi.asic->asic_id = VOYAGER_CAT_ID; psi.asic->subaddr = VOYAGER_SUBADDR_HI; psi.module_addr = VOYAGER_PSI; psi.scan_path_connected = 0; \ outb(VOYAGER_CAT_END, CAT_CMD); /* Connect the PSI to the CAT Bus */ outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT); outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT); outb(VOYAGER_CAT_RUN, CAT_CMD); cat_disconnect(&psi, &psi_asic); /* Read the status. NOTE: Need to read *all* the PSI regs here * otherwise the cmn int will be reasserted */ for(i = 0; i < sizeof(psi_reg.regs); i++) { cat_read(&psi, &psi_asic, i, &((__u8 *)&psi_reg.regs)[i]); } outb(VOYAGER_CAT_END, CAT_CMD); if((psi_reg.regs.checkbit & 0x02) == 0) { psi_reg.regs.checkbit |= 0x02; cat_write(&psi, &psi_asic, 5, psi_reg.regs.checkbit); printk("VOYAGER RE-READ PSI\n"); goto re_read; } outb(VOYAGER_CAT_RUN, CAT_CMD); for(i = 0; i < sizeof(psi_reg.subregs); i++) { /* This looks strange, but the PSI doesn't do auto increment * correctly */ cat_subread(&psi, &psi_asic, VOYAGER_PSI_SUPPLY_REG + i, 1, &((__u8 *)&psi_reg.subregs)[i]); } outb(VOYAGER_CAT_END, CAT_CMD); #ifdef VOYAGER_CAT_DEBUG printk("VOYAGER PSI: "); for(i=0; i arch/i386/voyager/voyager_cat.c K 63911 O -rw-rw-r-- P arch/i386/voyager/voyager_cat.c ------------------------------------------------ == arch/i386/voyager/voyager_smp.c == New file: arch/i386/kernel/voyager_smp.c V 4 jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c D 1.0 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/voyager-2.5/arch/i386/kernel/voyager_smp.c K 53264 P arch/i386/kernel/voyager_smp.c R 34d3a1aeab4cdc5c X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/kernel/voyager_smp.c|20020224140213|53264|34d3a1aeab4cdc5c D 1.1 02/02/24 08:02:13-06:00 jejb@mulgrave.(none) +1964 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 3482 O -rw-rw-r-- P arch/i386/kernel/voyager_smp.c ------------------------------------------------ I0 1964 /* -*- mode: c; c-basic-offset: 8 -*- */ \ /* Copyright (C) 1999,2001 * * Author: J.E.J.Bottomley@HansenPartnership.com * * linux/arch/i386/kernel/voyager_smp.c * * This file provides all the same external entries as smp.c but uses * the voyager hal to provide the functionality */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include \ #include \ /* The global kernel spinlock */ spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED; \ /* variables used by voyager_thread.c */ int kvoyagerd_running = 0; DECLARE_COMPLETION(kvoyagerd_wait); \ /* TLB state -- visible externally, indexed physically */ struct tlb_state cpu_tlbstate[NR_CPUS] = {[0 ... NR_CPUS-1] = { &init_mm, 0 }}; \ /* CPU IRQ affinity -- set to all ones initially */ static unsigned long cpu_irq_affinity[NR_CPUS] = { [0 ... NR_CPUS-1] = ~0UL }; \ /* Set when the idlers are all forked - Set in main.c but not actually * used by any other parts of the kernel */ int smp_threads_ready = 0; \ /* per CPU data structure (for /proc/cpuinfo et al), visible externally * indexed physically */ struct cpuinfo_x86 cpu_data[NR_CPUS]; \ /* physical ID of the CPU used to boot the system */ unsigned char boot_cpu_id; \ /* which logical number maps to which CPU */ volatile int __cpu_logical_map[NR_CPUS]; \ /* which physical CPU maps to which logical number */ volatile int __cpu_number_map[NR_CPUS]; \ /* The memory line addresses for the Quad CPIs */ struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS]; \ /* The masks for the Extended VIC processors, filled in by cat_init */ __u32 voyager_extended_vic_processors = 0; \ /* Masks for the extended Quad processors which cannot be VIC booted */ __u32 voyager_allowed_boot_processors = 0; \ /* The mask for the Quad Processors (both extended and non-extended) */ __u32 voyager_quad_processors = 0; \ /* Total count of live CPUs, used in process.c to display * the CPU information and in irq.c for the per CPU irq * activity count. Finally exported by i386_ksyms.c */ int smp_num_cpus = 1; static int voyager_extended_cpus = 1; \ /* Have we found an SMP box - used by time.c to do the profiling interrupt for timeslicing; do not set to 1 until the per CPU timer interrupt is active */ int smp_found_config = 0; \ /* Used for the invalidate map that's also checked in the spinlock */ volatile unsigned long smp_invalidate_needed; \ /* Bitmask of currently online CPUs - used by setup.c for /proc/cpuinfo, visible externally but still physical */ unsigned long cpu_online_map = 0; \ /* Bitmask of CPUs present in the system - exported by i386_syms.c, used * by scheduler but indexed physically */ unsigned long cpu_present_map = 0; \ /* estimate of time used to flush the SMP-local cache - used in * processor affinity calculations */ cycles_t cacheflush_time = 0; \ /* The internal functions */ static void send_CPI(__u32 cpuset, __u8 cpi); static void ack_CPI(__u8 cpi); static int ack_QIC_CPI(__u8 cpi); static void ack_special_QIC_CPI(__u8 cpi); static void ack_VIC_CPI(__u8 cpi); static void send_CPI_allbutself(__u8 cpi); static void enable_vic_irq(unsigned int irq); static void disable_vic_irq(unsigned int irq); static unsigned int startup_vic_irq(unsigned int irq); static void enable_local_vic_irq(unsigned int irq); static void disable_local_vic_irq(unsigned int irq); static void before_handle_vic_irq(unsigned int irq); static void after_handle_vic_irq(unsigned int irq); static void set_vic_irq_affinity(unsigned int irq, unsigned long mask); static void ack_vic_irq(unsigned int irq); static void vic_enable_cpi(void); static void do_boot_cpu(__u8 cpuid); static void do_quad_bootstrap(void); \ int hard_smp_processor_id(void); \ /* Inline functions */ static inline void send_one_QIC_CPI(__u8 cpu, __u8 cpi) { voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi = (smp_processor_id() << 16) + cpi; } \ static inline void send_QIC_CPI(__u32 cpuset, __u8 cpi) { int i; \ for(i=0; i>3 &0x7 on the 32 way */ if(((cpuid >> 2) & 0x03) == i) /* don't lower our own mask! */ continue; \ /* masquerade as local Quad CPU */ outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID); /* enable the startup CPI */ outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1); /* restore cpu id */ outb(0, QIC_PROCESSOR_ID); } __restore_flags(flags); } } \ \ /* Set up all the basic stuff: read the SMP config and make all the * SMP information reflect only the boot cpu. All others will be * brought on-line later. */ void __init find_smp_config(void) { int i; \ boot_cpu_id = hard_smp_processor_id(); \ printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id); \ /* initialize the CPU structures (moved from smp_boot_cpus) */ for(i=0; ipte_quick = 0; c->pmd_quick = 0; c->pgd_quick = 0; c->pgtable_cache_sz = 0; identify_cpu(c); } \ /* set up the trampoline and return the physical address of the code */ static __u32 __init setup_trampoline(void) { /* these two are global symbols in trampoline.S */ extern __u8 trampoline_end[]; extern __u8 trampoline_data[]; \ memcpy((__u8 *)trampoline_base, trampoline_data, trampoline_end - trampoline_data); return virt_to_phys((__u8 *)trampoline_base); } \ /* Routine initially called when a non-boot CPU is brought online */ int __init start_secondary(void *unused) { __u8 cpuid = hard_smp_processor_id(); /* external functions not defined in the headers */ extern void calibrate_delay(void); extern int cpu_idle(void); \ cpu_init(); \ /* OK, we're in the routine */ ack_CPI(VIC_CPU_BOOT_CPI); \ /* setup the 8259 master slave pair belonging to this CPU --- * we won't actually receive any until the boot CPU * relinquishes it's static routing mask */ vic_setup_pic(); \ qic_setup(); \ if(is_cpu_quad() && !is_cpu_vic_boot()) { /* clear the boot CPI */ __u8 dummy; \ dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi; printk("read dummy %d\n", dummy); } \ /* lower the mask to receive CPIs */ vic_enable_cpi(); \ VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid)); \ /* enable interrupts */ sti(); \ #ifdef CONFIG_MTRR /* * Must be done before calibration delay is computed */ mtrr_init_secondary_cpu (); #endif /* get our bogomips */ calibrate_delay(); \ /* save our processor parameters */ smp_store_cpu_info(cpuid); \ /* if we're a quad, we may need to bootstrap other CPUs */ do_quad_bootstrap(); \ VDEBUG(("VOYAGER DEBUG LOGICAL CPU%d, PHYS CPU%d: set cpu_booted_map going into spin\n", __cpu_number_map[cpuid], __cpu_logical_map[cpucount])); \ /* signal that we're done */ cpu_booted_map = 1; \ while(!atomic_read(&smp_commenced)) rep_nop(); \ local_flush_tlb(); return cpu_idle(); } \ static int __init fork_by_hand(void) { struct pt_regs regs; /* don't care about the eip and regs settings since we'll * never reschedule the forked task. */ return do_fork(CLONE_VM|CLONE_PID, 0, ®s, 0); } \ \ /* Routine to kick start the given CPU and wait for it to report ready * (or timeout in startup). When this routine returns, the requested * CPU is either fully running and configured or known to be dead. * * We call this routine sequentially 1 CPU at a time, so no need for * locking */ \ static void __init do_boot_cpu(__u8 cpu) { struct task_struct *idle; int timeout; unsigned long flags; int quad_boot = (1<> 4) & 0xFFFF; \ cpucount++; if(fork_by_hand() < 0) panic("failed fork for CPU%d", cpu); \ idle = init_task.prev_task; if (!idle) panic("No idle process for CPU %d", cpu); idle->processor = cpu; __cpu_logical_map[cpucount] = cpu; __cpu_number_map[cpu] = cpucount; idle->cpus_runnable = 1 << cpu; /* we schedule the first task manually */ idle->thread.eip = (unsigned long) start_secondary; del_from_runqueue(idle); unhash_process(idle); /* init_tasks (in sched.c) is indexed logically */ init_tasks[cpucount] = idle; #if 0 // for AC kernels stack_start.esp = (THREAD_SIZE + (__u8 *)TSK_TO_KSTACK(idle)); #else stack_start.esp = (void *) (1024 + PAGE_SIZE + (char *)idle); #endif /* Note: Don't modify initial ss override */ VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu, (unsigned long)hijack_source.val, hijack_source.idt.Segment, hijack_source.idt.Offset, stack_start.esp)); /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently * (so that the booting CPU can find start_32 */ orig_swapper_pg_dir0 = swapper_pg_dir[0]; #ifdef CONFIG_M486 if(page_table_copies == NULL) panic("No free memory for 486 page tables\n"); for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++) page_table_copies[i] = (i * PAGE_SIZE) | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; \ ((unsigned long *)swapper_pg_dir)[0] = ((virt_to_phys(page_table_copies)) & PAGE_MASK) | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; #else ((unsigned long *)swapper_pg_dir)[0] = 0x102007; #endif \ if(quad_boot) { printk("CPU %d: non extended Quad boot\n", cpu); hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4); *hijack_vector = hijack_source.val; } else { printk("CPU%d: extended VIC boot\n", cpu); hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4); *hijack_vector = hijack_source.val; /* VIC errata, may also receive interrupt at this address */ hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4); *hijack_vector = hijack_source.val; } /* All non-boot CPUs start with interrupts fully masked. Need * to lower the mask of the CPI we're about to send. We do * this in the VIC by masquerading as the processor we're * about to boot and lowering its interrupt mask */ __save_flags(flags); __cli(); if(quad_boot) { send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI); } else { outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID); /* here we're altering registers belonging to `cpu' */ outb(VIC_BOOT_INTERRUPT_MASK, 0x21); /* now go back to our original identity */ outb(boot_cpu_id, VIC_PROCESSOR_ID); \ /* and boot the CPU */ \ send_CPI((1<processor = boot_cpu_id; init_idle(); /* FIXME: Need to do something about this but currently only works * on CPUs with a tsc which none of mine have. smp_tune_scheduling(); */ smp_store_cpu_info(boot_cpu_id); printk("CPU%d: ", boot_cpu_id); print_cpu_info(&cpu_data[boot_cpu_id]); \ if(is_cpu_quad()) { /* booting on a Quad CPU */ printk("VOYAGER SMP: Boot CPU is Quad\n"); qic_setup(); do_quad_bootstrap(); } \ /* enable our own CPIs */ vic_enable_cpi(); /* loop over all the extended VIC CPUs and boot them. The * Quad CPUs must be bootstrapped by their extended VIC cpu */ for(i = 0; i < NR_CPUS; i++) { if( i == boot_cpu_id || ((1<thread.esp),"r" (current->thread.eip)); } \ /* handle a Voyager SYS_INT -- If we don't, the base board will * panic the system. * * System interrupts occur because some problem was detected on the * various busses. To find out what you have to probe all the * hardware via the CAT bus. FIXME: At the moment we do nothing. */ asmlinkage void smp_vic_sys_interrupt(void) { ack_CPI(VIC_SYS_INT); printk("Voyager SYSTEM INTERRUPT\n"); } \ /* Handle a voyager CMN_INT; These interrupts occur either because of * a system status change or because a single bit memory error * occurred. FIXME: At the moment, ignore all this. */ asmlinkage void smp_vic_cmn_interrupt(void) { static __u8 in_cmn_int = 0; static spinlock_t cmn_int_lock = SPIN_LOCK_UNLOCKED; \ /* common ints are broadcast, so make sure we only do this once */ spin_lock(&cmn_int_lock); if(in_cmn_int) goto unlock_end; \ in_cmn_int++; spin_unlock(&cmn_int_lock); \ VDEBUG(("Voyager COMMON INTERRUPT\n")); \ if(voyager_level == 5) voyager_cat_do_common_interrupt(); \ spin_lock(&cmn_int_lock); in_cmn_int = 0; unlock_end: spin_unlock(&cmn_int_lock); ack_CPI(VIC_CMN_INT); } \ /* * Reschedule call back. Nothing to do, all the work is done * automatically when we return from the interrupt. */ asmlinkage void smp_reschedule_interrupt(void) { /* do nothing */ } \ static struct mm_struct * flush_mm; static unsigned long flush_va; static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED; #define FLUSH_ALL 0xffffffff \ /* * We cannot call mmdrop() because we are in interrupt context, * instead update mm->cpu_vm_mask. */ static void inline leave_mm (unsigned long cpu) { if (cpu_tlbstate[cpu].state == TLBSTATE_OK) BUG(); clear_bit(cpu, &cpu_tlbstate[cpu].active_mm->cpu_vm_mask); } \ \ /* * Invalidate call-back */ asmlinkage void smp_invalidate_interrupt(void) { __u8 cpu = smp_processor_id(); \ if(!test_bit(cpu, &smp_invalidate_needed)) return; /* This will flood messages. Don't uncomment unless you see * Problems with cross cpu invalidation VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n", smp_processor_id())); */ \ if (flush_mm == cpu_tlbstate[cpu].active_mm) { if (cpu_tlbstate[cpu].state == TLBSTATE_OK) { if (flush_va == FLUSH_ALL) local_flush_tlb(); else __flush_tlb_one(flush_va); } else leave_mm(cpu); } clear_bit(cpu, &smp_invalidate_needed); } \ /* All the new flush operations for 2.4 */ \ \ /* This routine is called with a physical cpu mask */ static void flush_tlb_others (unsigned long cpumask, struct mm_struct *mm, unsigned long va) { int stuck = 50000; \ if (!cpumask) BUG(); if ((cpumask & cpu_online_map) != cpumask) BUG(); if (cpumask & (1 << smp_processor_id())) BUG(); if (!mm) BUG(); \ spin_lock(&tlbstate_lock); flush_mm = mm; flush_va = va; atomic_set_mask(cpumask, &smp_invalidate_needed); /* * We have to send the CPI only to * CPUs affected. */ send_CPI(cpumask, VIC_INVALIDATE_CPI); \ while (smp_invalidate_needed) { if(--stuck == 0) { printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id()); break; } } \ /* Uncomment only to debug invalidation problems VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu)); */ \ flush_mm = NULL; flush_va = 0; spin_unlock(&tlbstate_lock); } \ void flush_tlb_current_task(void) { struct mm_struct *mm = current->mm; unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id()); \ local_flush_tlb(); if (cpu_mask) flush_tlb_others(cpu_mask, mm, FLUSH_ALL); } \ \ void flush_tlb_mm (struct mm_struct * mm) { unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id()); \ if (current->active_mm == mm) { if (current->mm) local_flush_tlb(); else leave_mm(smp_processor_id()); } if (cpu_mask) flush_tlb_others(cpu_mask, mm, FLUSH_ALL); } \ void flush_tlb_page(struct vm_area_struct * vma, unsigned long va) { struct mm_struct *mm = vma->vm_mm; unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id()); \ if (current->active_mm == mm) { if(current->mm) __flush_tlb_one(va); else leave_mm(smp_processor_id()); } \ if (cpu_mask) flush_tlb_others(cpu_mask, mm, va); } \ /* enable the requested IRQs */ asmlinkage void smp_enable_irq_interrupt(void) { __u8 irq; __u8 cpu = smp_processor_id(); \ VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu, vic_irq_enable_mask[cpu])); \ spin_lock(&vic_irq_lock); for(irq = 0; irq < 16; irq++) { if(vic_irq_enable_mask[cpu] & (1<func; void *info = call_data->info; /* must take copy of wait because call_data may be replaced * unless the function is waiting for us to finish */ int wait = call_data->wait; __u8 cpu = smp_processor_id(); \ /* * Notify initiating CPU that I've grabbed the data and am * about to execute the function */ if(!test_and_clear_bit(cpu, &call_data->started)) { /* If the bit wasn't set, this could be a replay */ printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu); return; } /* * At this point the info structure may be out of scope unless wait==1 */ (*func)(info); if (wait) clear_bit(cpu, &call_data->finished); } \ /* Call this function on all CPUs using the function_interrupt above The function to run. This must be fast and non-blocking. An arbitrary pointer to pass to the function. If true, keep retrying until ready. If true, wait until function has completed on other CPUs. [RETURNS] 0 on success, else a negative status code. Does not return until remote CPUs are nearly ready to execute <> or are or have executed. */ int smp_call_function (void (*func) (void *info), void *info, int retry, int wait) { struct call_data_struct data; __u32 mask = cpu_online_map; \ mask &= ~(1<= 0x93000) BUG(); } \ /* send a reschedul