Index: linux/2.4/MAINTAINERS diff -u linux/2.4/MAINTAINERS:1.1.1.11 linux/2.4/MAINTAINERS:1.1.1.11.2.1 --- linux/2.4/MAINTAINERS:1.1.1.11 Sat Mar 31 15:43:47 2001 +++ linux/2.4/MAINTAINERS Sat Mar 31 16:41:00 2001 @@ -742,6 +742,12 @@ L: linux-x25@vger.kernel.org S: Maintained +LINUX FOR NCR VOYAGER +P: James Bottomley +M: J.E.J.Bottomley@HansenPartnership.com +W: http://www.hansenpartnership.com/voyager +S: Maintained + LINUX FOR POWERPC P: Cort Dougan M: cort@fsmlabs.com Index: linux/2.4/Documentation/Configure.help diff -u linux/2.4/Documentation/Configure.help:1.1.1.11 linux/2.4/Documentation/Configure.help:1.1.1.11.2.1 --- linux/2.4/Documentation/Configure.help:1.1.1.11 Sat Mar 31 15:47:43 2001 +++ linux/2.4/Documentation/Configure.help Sat Mar 31 16:41:00 2001 @@ -2621,6 +2621,16 @@ Otherwise, say N. +Support for the NCR Voyager Architecture +CONFIG_VOYAGER + Voyager is a MCA based 32 way capable SMP architecture proprietary + to NCR Corp. Machine classes 345x/35xx/51xx are voyager based. + + *** WARNING *** + + If you do not specifically know you have a Voyager based machine, + say N here otherwise the kernel you build will not be bootable. + SGI Visual Workstation support CONFIG_VISWS The SGI Visual Workstation series is an IA32-based workstation Index: linux/2.4/Documentation/voyager.txt diff -u /dev/null linux/2.4/Documentation/voyager.txt:1.1.12.1 --- /dev/null Sat Mar 31 18:39:32 2001 +++ linux/2.4/Documentation/voyager.txt Sat Mar 31 16:41:01 2001 @@ -0,0 +1,84 @@ +Running Linux on the Voyager Architecture +========================================= + +For full details and current project status, see + +http://www.hansenpartnership.com/voyager + +The voyager architecture was designed by NCR in the mid 80s to be a +fully SMP capable RAS computing architecture built around intel's 486 +chip set. The voyager came in three levels of architectural +sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype. +The linux patches support only the Level 5 voyager architecture (any +machine class 3435 and above). + +The Voyager Architecture +------------------------ + +Voyager machines consist of a Baseboard with a 386 diagnostic +processor, a Power Supply Interface (PSI) a Primary and possibly +Secondary Microchannel bus and between 2 and 20 voyager slots. The +voyager slots can be populated with memory and cpu cards (up to 4GB +memory and from 1 486 to 32 Pentium Pro processors). Internally, the +voyager has a dual arbitrated system bus and a configuration and test +bus (CAT). The voyager bus speed is 40MHz. Therefore (since all +voyager cards are dual ported for each system bus) the maximum +transfer rate is 320Mb/s but only if you have your slot configuration +tuned (only memory cards can communicate with both busses at once, CPU +cards utilise them one at a time). + +Voyager SMP +----------- + +Since voyager was the first intel based SMP system, it is slightly +more primitive than the Intel IO-APIC approach to SMP. Voyager allows +arbitrary interrupt routing (including processor affinity routing) of +all 16 PC type interrupts. However it does this by using a modified +5259 master/slave chip set instead of an APIC bus. Additionally, +voyager supports Cross Processor Interrupts (CPI) equivalent to the +APIC IPIs. There are two routed voyager interrupt lines provided to +each slot. + +Processor Cards +--------------- + +These come in single, dyadic and quad configurations (the quads are +problematic--see later). The maximum configuration is 8 quad cards +for 32 way SMP. + +Quad Processors +--------------- + +Because voyager only supplies two interrupt lines to each Processor +card, the Quad processors have to be configured (and Bootstrapped) in +as a pair of Master/Slave processors. + +In fact, most Quad cards only accept one VIC interrupt line, so they +have one interrupt handling processor (called the VIC extended +processor) and three non-interrupt handling processors. + +Current Status +-------------- + +The System will boot on Mono, Dyad and Quad cards. There was +originally a Quad boot problem which has been fixed by proper gdt +alignment in the initial boot loader. If you still cannot get your +voyager system to boot, email me at: + + + + +The Quad cards now support using the separate Quad CPI vectors instead +of going through the VIC mailbox system. + +The Level 4 architecture (3430 and 3360 Machines) seems to work, as +long as you specify memory size and don't expect any of the machine +specific functions (reboot, power off etc.) to work. + +A Note About Mixed CPU Systems +------------------------------ + +Linux isn't designed to handle mixed CPU systems very well. In order +to get everything going you *must* make sure that your lowest +capability CPU is used for booting. Also, mixing CPU classes +(e.g. 486 and 586) is really not going to work very well at all. Index: linux/2.4/arch/i386/config.in diff -u linux/2.4/arch/i386/config.in:1.1.1.8 linux/2.4/arch/i386/config.in:1.1.1.8.2.1 --- linux/2.4/arch/i386/config.in:1.1.1.8 Sat Mar 31 15:46:58 2001 +++ linux/2.4/arch/i386/config.in Sat Mar 31 16:41:01 2001 @@ -173,12 +173,22 @@ bool 'Networking support' CONFIG_NET bool 'SGI Visual Workstation support' CONFIG_VISWS + +if [ "$CONFIG_VISWS" != "y" ]; then + bool 'MCA support' CONFIG_MCA + if [ "$CONFIG_MCA" = "y" ]; then + bool ' Support for the NCR Voyager Architecture' CONFIG_VOYAGER + fi +else + define_bool CONFIG_MCA n +fi + if [ "$CONFIG_VISWS" = "y" ]; then define_bool CONFIG_X86_VISWS_APIC y define_bool CONFIG_X86_LOCAL_APIC y define_bool CONFIG_PCI y else - if [ "$CONFIG_SMP" = "y" ]; then + if [ "$CONFIG_SMP" = "y" -a "$CONFIG_VOYAGER" != "y" ]; then define_bool CONFIG_X86_IO_APIC y define_bool CONFIG_X86_LOCAL_APIC y fi @@ -200,12 +210,6 @@ source drivers/pci/Config.in bool 'EISA support' CONFIG_EISA - -if [ "$CONFIG_VISWS" != "y" ]; then - bool 'MCA support' CONFIG_MCA -else - define_bool CONFIG_MCA n -fi bool 'Support for hot-pluggable devices' CONFIG_HOTPLUG Index: linux/2.4/arch/i386/boot/setup.S diff -u linux/2.4/arch/i386/boot/setup.S:1.1.1.7 linux/2.4/arch/i386/boot/setup.S:1.1.1.7.2.1 --- linux/2.4/arch/i386/boot/setup.S:1.1.1.7 Sat Mar 31 15:46:58 2001 +++ linux/2.4/arch/i386/boot/setup.S Sat Mar 31 16:41:01 2001 @@ -444,6 +444,24 @@ movsb popw %ds no_mca: +#ifdef CONFIG_VOYAGER + movb $0xff, 0x40 # flag on config found + movb $0xc0, %al + mov $0xff, %ah + int $0x15 # put voyager config info at es:di + jc no_voyager + movw $0x40, %si # place voyager info in apm table + cld + movw $7, %cx +voyager_rep: + movb %es:(%di), %al + movb %al,(%si) + incw %di + incw %si + decw %cx + jnz voyager_rep +no_voyager: +#endif # Check for PS/2 pointing device movw %cs, %ax # aka SETUPSEG subw $DELTA_INITSEG, %ax # aka INITSEG @@ -881,6 +899,13 @@ ret # Descriptor tables + +## +# NOTE: On some CPUs, the GDT must be 8 byte aligned. This is +# true for the Voyager Quad CPU card which will not boot without +# This directive. +## + .align 8 gdt: .word 0, 0, 0, 0 # dummy .word 0, 0, 0, 0 # unused Index: linux/2.4/arch/i386/kernel/Makefile diff -u linux/2.4/arch/i386/kernel/Makefile:1.1.1.5 linux/2.4/arch/i386/kernel/Makefile:1.1.1.5.2.1 --- linux/2.4/arch/i386/kernel/Makefile:1.1.1.5 Sat Mar 31 15:46:59 2001 +++ linux/2.4/arch/i386/kernel/Makefile Sat Mar 31 16:41:02 2001 @@ -31,12 +31,17 @@ endif obj-$(CONFIG_MCA) += mca.o +obj-$(CONFIG_VOYAGER) += voyager.o voyager_cat.o obj-$(CONFIG_MTRR) += mtrr.o obj-$(CONFIG_X86_MSR) += msr.o obj-$(CONFIG_X86_CPUID) += cpuid.o obj-$(CONFIG_MICROCODE) += microcode.o obj-$(CONFIG_APM) += apm.o +ifdef CONFIG_VOYAGER +obj-$(CONFIG_SMP) += voyager_smp.o trampoline.o +else obj-$(CONFIG_SMP) += smp.o smpboot.o trampoline.o +endif obj-$(CONFIG_X86_LOCAL_APIC) += apic.o obj-$(CONFIG_X86_IO_APIC) += io_apic.o mpparse.o obj-$(CONFIG_X86_VISWS_APIC) += visws_apic.o Index: linux/2.4/arch/i386/kernel/head.S diff -u linux/2.4/arch/i386/kernel/head.S:1.1.1.4 linux/2.4/arch/i386/kernel/head.S:1.1.1.4.4.1 --- linux/2.4/arch/i386/kernel/head.S:1.1.1.4 Wed Mar 28 18:00:38 2001 +++ linux/2.4/arch/i386/kernel/head.S Sat Mar 31 16:41:02 2001 @@ -53,7 +53,7 @@ movl %eax,%es movl %eax,%fs movl %eax,%gs -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && !defined(CONFIG_M486) orw %bx,%bx jz 1f Index: linux/2.4/arch/i386/kernel/i386_ksyms.c diff -u linux/2.4/arch/i386/kernel/i386_ksyms.c:1.1.1.8 linux/2.4/arch/i386/kernel/i386_ksyms.c:1.1.1.8.2.1 --- linux/2.4/arch/i386/kernel/i386_ksyms.c:1.1.1.8 Sat Mar 31 15:47:00 2001 +++ linux/2.4/arch/i386/kernel/i386_ksyms.c Sat Mar 31 16:41:02 2001 @@ -162,3 +162,9 @@ #ifdef CONFIG_X86_PAE EXPORT_SYMBOL(empty_zero_page); #endif + +#ifdef CONFIG_VOYAGER +/* need to export the mappings from physical to logical CPU */ +EXPORT_SYMBOL(__cpu_number_map); +EXPORT_SYMBOL(__cpu_logical_map); +#endif Index: linux/2.4/arch/i386/kernel/i8259.c diff -u linux/2.4/arch/i386/kernel/i8259.c:1.1.1.6 linux/2.4/arch/i386/kernel/i8259.c:1.1.1.6.2.1 --- linux/2.4/arch/i386/kernel/i8259.c:1.1.1.6 Sat Mar 31 15:47:00 2001 +++ linux/2.4/arch/i386/kernel/i8259.c Sat Mar 31 16:41:02 2001 @@ -19,6 +19,9 @@ #include #include #include +#ifdef CONFIG_VOYAGER +#include +#endif #include @@ -50,7 +53,7 @@ */ BUILD_16_IRQS(0x0) -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_VOYAGER) /* * The IO-APIC gives us many more interrupt sources. Most of these * are unused but an SMP system is supposed to have enough memory ... @@ -76,7 +79,7 @@ * is no hardware IRQ pin equivalent for them, they are triggered * through the ICC by us (IPIs) */ -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && !defined(CONFIG_VOYAGER) BUILD_SMP_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR) BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR) BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR) @@ -107,7 +110,7 @@ void (*interrupt[NR_IRQS])(void) = { IRQLIST_16(0x0), -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_VOYAGER) IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), @@ -456,6 +459,11 @@ } #ifdef CONFIG_SMP +#ifdef CONFIG_VOYAGER + + /* set up voyager SMP interrupts */ + voyager_smp_intr_init(); +#else /* * IRQ0 must be given a fixed assignment and initialized, * because it's used before the IO-APIC is set up. @@ -482,6 +490,7 @@ /* IPI vectors for APIC spurious and error interrupts */ set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); +#endif /* CONFIG_VOYAGER */ #endif /* Index: linux/2.4/arch/i386/kernel/irq.c diff -u linux/2.4/arch/i386/kernel/irq.c:1.1.1.8 linux/2.4/arch/i386/kernel/irq.c:1.1.1.8.2.2 --- linux/2.4/arch/i386/kernel/irq.c:1.1.1.8 Sat Mar 31 15:46:59 2001 +++ linux/2.4/arch/i386/kernel/irq.c Sat Mar 31 18:37:54 2001 @@ -133,7 +133,7 @@ p += sprintf(p, " "); for (j=0; j #include #include +#ifdef CONFIG_VOYAGER +#include +#endif #include #include @@ -150,7 +153,9 @@ __setup("idle=", idle_setup); +#ifndef CONFIG_VOYAGER static long no_idt[2]; +#endif static int reboot_mode; static int reboot_thru_bios; @@ -181,6 +186,7 @@ __setup("reboot=", reboot_setup); +#ifndef CONFIG_VOYAGER /* The following code and data reboots the machine by switching to real mode and jumping to the BIOS reset entry point, as if the CPU has really been reset. The previous version asked the keyboard @@ -241,6 +247,7 @@ { 0xea, 0x00, 0x00, 0xff, 0xff /* ljmp $0xffff,$0x0000 */ }; +#endif /* CONFIG VOYAGER */ static inline void kb_wait(void) { @@ -260,6 +267,21 @@ { unsigned long flags; +#ifdef CONFIG_VOYAGER + printk("Voyager Warm Restart\n"); + kb_wait(); + /* write magic values to the RTC to inform system that + * shutdown is beginning */ + outb(0x8f, 0x70); + outb(0x5 , 0x71); + + udelay(50); + outb(0xfe,0x64); /* pull reset low */ + for(;;) { + asm("cli"); + asm("hlt"); + } +#else cli(); /* Write zero to CMOS register number 0x0f, which the BIOS POST @@ -341,10 +363,14 @@ __asm__ __volatile__ ("ljmp $0x0008,%0" : : "i" ((void *) (0x1000 - sizeof (real_mode_switch) - 100))); +#endif /* CONFIG_VOYAGER */ } void machine_restart(char * __unused) { +#ifdef CONFIG_VOYAGER + machine_real_restart(NULL, 0); +#else #if CONFIG_SMP /* * Stop all CPUs and turn off local APICs and the IO-APIC, so @@ -372,16 +398,30 @@ } machine_real_restart(jump_to_bios, sizeof(jump_to_bios)); +#endif /* CONFIG_VOYAGER */ } void machine_halt(void) { +#ifdef CONFIG_VOYAGER + /* treat a halt like a power off */ + machine_power_off(); +#endif } void machine_power_off(void) { +#ifdef CONFIG_VOYAGER +#ifdef CONFIG_SMP + smp_call_function(smp_voyager_power_off, NULL, 1, 1); + smp_voyager_power_off(NULL); +#else + voyager_power_off(); +#endif +#else if (pm_power_off) pm_power_off(); +#endif } extern void show_trace(unsigned long* esp); Index: linux/2.4/arch/i386/kernel/setup.c diff -u linux/2.4/arch/i386/kernel/setup.c:1.1.1.11 linux/2.4/arch/i386/kernel/setup.c:1.1.1.11.2.1 --- linux/2.4/arch/i386/kernel/setup.c:1.1.1.11 Sat Mar 31 15:46:59 2001 +++ linux/2.4/arch/i386/kernel/setup.c Sat Mar 31 16:41:02 2001 @@ -80,6 +80,9 @@ #include #include #include +#ifdef CONFIG_VOYAGER +#include +#endif #ifdef CONFIG_BLK_DEV_RAM #include #endif @@ -119,6 +122,9 @@ unsigned int machine_id; unsigned int machine_submodel_id; unsigned int BIOS_revision; +#ifdef CONFIG_VOYAGER +struct voyager_bios_info voyager_bios_info; +#endif unsigned int mca_pentium_flag; /* @@ -158,7 +164,11 @@ #define ALT_MEM_K (*(unsigned long *) (PARAM+0x1e0)) #define E820_MAP_NR (*(char*) (PARAM+E820NR)) #define E820_MAP ((struct e820entry *) (PARAM+E820MAP)) +#ifdef CONFIG_VOYAGER +#define VOYAGER_BIOS_INFO (*(struct voyager_bios_info *)(PARAM+0x40)) +#else #define APM_BIOS_INFO (*(struct apm_bios_info *) (PARAM+0x40)) +#endif #define DRIVE_INFO (*(struct drive_info_struct *) (PARAM+0x80)) #define SYS_DESC_TABLE (*(struct sys_desc_table_struct*)(PARAM+0xa0)) #define MOUNT_ROOT_RDONLY (*(unsigned short *) (PARAM+0x1F2)) @@ -455,6 +465,7 @@ * thinkpad 560x, for example, does not cooperate with the memory * detection code.) */ +#ifndef CONFIG_VOYAGER static int __init copy_e820_map(struct e820entry * biosmap, int nr_map) { /* Only one memory region (or negative)? Ignore it */ @@ -489,7 +500,7 @@ } while (biosmap++,--nr_map); return 0; } - +#endif /* CONFIG_VOYAGER */ /* * Do NOT EVER look at the BIOS memory size location. * It does not work on many machines. @@ -498,6 +509,17 @@ void __init setup_memory_region(void) { +#ifdef CONFIG_VOYAGER + char *who = "Voyager-SUS"; + __u32 addr, length; + int i; + + e820.nr_map = 0; + for(i=0; voyager_memory_detect(i, &addr, &length); i++) { + add_memory_region(addr, length, E820_RAM); + } + +#else char *who = "BIOS-e820"; /* @@ -522,6 +544,7 @@ add_memory_region(0, LOWMEMSIZE(), E820_RAM); add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM); } +#endif /* CONFIG_VOYAGER */ printk(KERN_INFO "BIOS-provided physical RAM map:\n"); print_memory_map(who); } /* setup_memory_region */ @@ -610,7 +633,6 @@ ROOT_DEV = to_kdev_t(ORIG_ROOT_DEV); drive_info = DRIVE_INFO; screen_info = SCREEN_INFO; - apm_info.bios = APM_BIOS_INFO; if( SYS_DESC_TABLE.length != 0 ) { MCA_bus = SYS_DESC_TABLE.table[3] &0x2; machine_id = SYS_DESC_TABLE.table[0]; @@ -624,8 +646,34 @@ rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0); rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0); #endif +#ifdef CONFIG_VOYAGER + voyager_bios_info = VOYAGER_BIOS_INFO; + if(voyager_bios_info.len != 0xff) { + int class = (voyager_bios_info.class_1 << 8) + | (voyager_bios_info.class_2 & 0xff); + int level; + + printk("Voyager System detected.\n\tClass %x, Revision %d.%d\n", + class, voyager_bios_info.major, + voyager_bios_info.minor); + if(class == VOYAGER_LEVEL4) + level = 4; + else if(class < VOYAGER_LEVEL5_AND_ABOVE) + level = 3; + else + level = 5; + printk("\tArchitecture Level %d\n", level); + if(level < 5) + printk("\n**WARNING**: Voyager HAL only supports Level5 Architectures at the moment\n\n"); + } + else { + printk("\n\n**WARNING**: No Voyager Subsystem Found\n"); + } + +#else + apm_info.bios = APM_BIOS_INFO; +#endif /* CONFIG_VOYAGER */ setup_memory_region(); - if (!MOUNT_ROOT_RDONLY) root_mountflags &= ~MS_RDONLY; init_mm.start_code = (unsigned long) &_text; @@ -772,7 +820,7 @@ smp_alloc_memory(); /* AP processor realmode stacks in low memory*/ #endif -#ifdef CONFIG_X86_IO_APIC +#if defined(CONFIG_X86_IO_APIC) || defined (CONFIG_VOYAGER) /* * Find and reserve possible boot-time SMP configuration: */ Index: linux/2.4/arch/i386/kernel/time.c diff -u linux/2.4/arch/i386/kernel/time.c:1.1.1.6 linux/2.4/arch/i386/kernel/time.c:1.1.1.6.2.1 --- linux/2.4/arch/i386/kernel/time.c:1.1.1.6 Sat Mar 31 15:47:00 2001 +++ linux/2.4/arch/i386/kernel/time.c Sat Mar 31 16:41:02 2001 @@ -58,6 +58,10 @@ #include #include +#ifdef CONFIG_VOYAGER +#include +#endif + /* * for x86_do_profile() */ @@ -196,7 +200,16 @@ if( jiffies_t == jiffies_p ) { if( count > count_p ) { /* the nutcase */ - +#if defined(CONFIG_VOYAGER) && defined(CONFIG_SMP) + /* can't read the ISR, just assume 1 tick + overflow */ + if(count > LATCH || count < 0) { + printk("VOYAGER PROBLEM: count is %ld, latch is %ld\n", count, LATCH); + count = LATCH; + } + count -= LATCH; +#else + int i; spin_lock(&i8259A_lock); @@ -230,6 +243,7 @@ printk("do_slow_gettimeoffset(): hardware timer problem?\n"); #endif } +#endif /* CONFIG_VOYAGER && CONFIG_SMP */ } } else jiffies_p = jiffies_t; @@ -409,6 +423,9 @@ * profiling, except when we simulate SMP mode on a uniprocessor * system, in that case we have to call the local interrupt handler. */ +#ifdef CONFIG_VOYAGER + voyager_timer_interrupt(regs); +#else #ifndef CONFIG_X86_LOCAL_APIC if (!user_mode(regs)) x86_do_profile(regs->eip); @@ -416,6 +433,7 @@ if (!smp_found_config) smp_local_timer_interrupt(regs); #endif +#endif /* * If we have an externally synchronized Linux clock, then update @@ -644,6 +662,10 @@ * to disk; this won't break the kernel, though, 'cuz we're * smart. See arch/i386/kernel/apm.c. */ +#ifndef CONFIG_VOYAGER + /* For voyager, even if some of our CPUs have a TSC, they can + * be driven by different clocks, so the TSCs will drift out + * of sync. It is much safer to use the slow gettimeoffset */ /* * Firstly we have to do a CPU check for chips with * a potentially buggy TSC. At this point we haven't run @@ -685,6 +707,7 @@ } } } +#endif #ifdef CONFIG_VISWS printk("Starting Cobalt Timer system clock\n"); Index: linux/2.4/arch/i386/kernel/voyager.c diff -u /dev/null linux/2.4/arch/i386/kernel/voyager.c:1.1.12.1 --- /dev/null Sat Mar 31 18:39:43 2001 +++ linux/2.4/arch/i386/kernel/voyager.c Sat Mar 31 16:41:02 2001 @@ -0,0 +1,178 @@ +/* Copyright (C) 1999,2001 + * + * Author: J.E.J.Bottomley@HansenPartnership.com + * + * linux/arch/i386/kernel/voyager.c + * + * This file contains all the voyager specific routines for getting + * initialisation of the architecture to function. For additional + * features see: + * + * voyager_cat.c - Voyager CAT bus interface + * voyager_smp.c - Voyager SMP hal (emulates linux smp.c) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +void +voyager_system_interrupt(int cpl, void *dev_id, struct pt_regs *regs) +{ + printk("Voyager: detected system interrupt\n"); +} + +/* Routine to read information from the extended CMOS area */ +__u8 +voyager_extended_cmos_read(__u16 addr) +{ + outb(addr & 0xff, 0x74); + outb((addr >> 8) & 0xff, 0x75); + return inb(0x76); +} + +/* internal definitions for the SUS Click Map of memory */ + +#define CLICK_ENTRIES 16 +#define CLICK_SIZE 4096 /* click to byte conversion for Length */ + +typedef struct ClickMap { + struct Entry { + __u32 Address; + __u32 Length; + } Entry[CLICK_ENTRIES]; +} ClickMap_t; + + +/* This routine is pretty much an awful hack to read the bios clickmap by + * mapping it into page 0. There are usually three regions in the map: + * Base Memory + * Extended Memory + * zero length marker for end of map + * + * Returns are 0 for failure and 1 for success on extracting region. + */ +int __init +voyager_memory_detect(int region, __u32 *start, __u32 *length) +{ + int i; + int retval = 0; + __u8 cmos[4]; + ClickMap_t *map; + unsigned long map_addr; + unsigned long old; + + if(region >= CLICK_ENTRIES) { + printk("Voyager: Illegal ClickMap region %d\n", region); + return 0; + } + + for(i = 0; i < sizeof(cmos); i++) + cmos[i] = voyager_extended_cmos_read(VOYAGER_MEMORY_CLICKMAP + i); + + map_addr = *(unsigned long *)cmos; + + /* steal page 0 for this */ + old = pg0[0]; + pg0[0] = ((map_addr & PAGE_MASK) | _PAGE_RW | _PAGE_PRESENT); + local_flush_tlb(); + /* now clear everything out but page 0 */ + map = (ClickMap_t *)(map_addr & (~PAGE_MASK)); + + /* zero length is the end of the clickmap */ + if(map->Entry[region].Length != 0) { + *length = map->Entry[region].Length * CLICK_SIZE; + *start = map->Entry[region].Address; + retval = 1; + } + + /* replace the mapping */ + pg0[0] = old; + local_flush_tlb(); + return retval; +} + +void +voyager_dump() +{ + /* get here via a sysrq */ +#ifdef CONFIG_SMP + voyager_smp_dump(); +#endif +} + +/* voyager specific handling code for timer interrupts. Used to hand + * off the timer tick to the SMP code, since the VIC doesn't have an + * internal timer (The QIC does, but that's another story). */ +void +voyager_timer_interrupt(struct pt_regs *regs) +{ + if((jiffies & 0x3ff) == 0) { + + /* There seems to be something flaky in either + * hardware or software that is resetting the timer 0 + * count to something much higher than it should be + * This seems to occur in the boot sequence, just + * before root is mounted. Therefore, every 10 + * seconds or so, we sanity check the timer zero count + * and kick it back to where it should be. + * + * FIXME: This is the most awful hack yet seen. I + * should work out exactly what is interfering with + * the timer count settings early in the boot sequence + * and swiftly introduce it to something sharp and + * pointy. */ + __u16 val; + extern spinlock_t i8253_lock; + + spin_lock(&i8253_lock); + + outb_p(0x00, 0x43); + val = inb_p(0x40); + val |= inb(0x40) << 8; + spin_unlock(&i8253_lock); + + if(val > LATCH) { + printk("\nVOYAGER: countdown timer value too high (%d), resetting\n\n", val); + spin_lock(&i8253_lock); + outb(0x34,0x43); + outb_p(LATCH & 0xff , 0x40); /* LSB */ + outb(LATCH >> 8 , 0x40); /* MSB */ + spin_unlock(&i8253_lock); + } + } +#ifdef CONFIG_SMP + smp_vic_timer_interrupt(regs); +#endif +} + +void +voyager_power_off(void) +{ + int port; + + printk("VOYAGER Power Off\n"); + + __cli(); + + /* enable the voyager Configuration Space */ + outb((inb(0x96) & 0xf0) | 0x8, 0x96); + /* the port for the power off flag is an offset from the + floating base */ + port = inb(0x99) * 0x100 + 0x21; + /* set the power off flag */ + outb(inb(port) | 0x1, port); + /* and wait for it to happen */ + for(;;) + __asm("hlt"); +} Index: linux/2.4/arch/i386/kernel/voyager_cat.c diff -u /dev/null linux/2.4/arch/i386/kernel/voyager_cat.c:1.1.12.1 --- /dev/null Sat Mar 31 18:39:43 2001 +++ linux/2.4/arch/i386/kernel/voyager_cat.c Sat Mar 31 16:41:02 2001 @@ -0,0 +1,908 @@ +/* -*- mode: c; c-basic-offset: 8 -*- */ + +/* Copyright (C) 1999,2001 + * + * Author: J.E.J.Bottomley@HansenPartnership.com + * + * linux/arch/i386/kernel/voyager_cat.c + * + * This file contains all the logic for manipulating the CAT bus + * in a level 5 machine. + * + * The CAT bus is a serial configuration and test bus. Its primary + * uses are to probe the initial configuration of the system and to + * diagnose error conditions when a system interrupt occurs. The low + * level interface is fairly primitive, so most of this file consists + * of bit shift manipulations to send and receive packets on the + * serial bus */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef VOYAGER_CAT_DEBUG +#define CDEBUG(x) printk x +#else +#define CDEBUG(x) +#endif + +/* the CAT command port */ +#define CAT_CMD (sspb + 0xe) +/* the CAT data port */ +#define CAT_DATA (sspb + 0xd) + +/* the internal cat functions */ +static void cat_pack(__u8 *msg, __u16 start_bit, __u8 *data, + __u16 num_bits); +static void cat_unpack(__u8 *msg, __u16 start_bit, __u8 *data, + __u16 num_bits); +static void cat_build_header(__u8 *header, const __u16 len, + const __u16 smallest_reg_bits, + const __u16 longest_reg_bits); +static int cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, + __u8 reg, __u8 op); +static int cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, + __u8 reg, __u8 *value); +static int cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, + __u8 pad_bits); +static int cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, + __u8 value); +static int cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, + __u8 *value); +static int cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, + __u16 offset, __u16 len, void *buf); +static int cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp, + __u8 reg, __u8 value); +static int cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp); +static int cat_connect(voyager_module_t *modp, voyager_asic_t *asicp); + +static inline const char * +cat_module_name(int module_id) +{ + switch(module_id) { + case 0x10: + return "Processor Slot 0"; + case 0x11: + return "Processor Slot 1"; + case 0x12: + return "Processor Slot 2"; + case 0x13: + return "Processor Slot 4"; + case 0x14: + return "Memory Slot 0"; + case 0x15: + return "Memory Slot 1"; + case 0x18: + return "Primary Microchannel"; + case 0x19: + return "Secondary Microchannel"; + case 0x1a: + return "Power Supply Interface"; + case 0x1c: + return "Processor Slot 5"; + case 0x1d: + return "Processor Slot 6"; + case 0x1e: + return "Processor Slot 7"; + case 0x1f: + return "Processor Slot 8"; + default: + return "Unknown Module"; + } +} + +static int sspb = 0; + +voyager_module_t *voyager_cat_list; + +/* the I/O port assignments for the VIC and QIC */ +static struct resource vic_res = { + "Voyager Interrupt Controller", 0xFC00, 0xFC6F }; +static struct resource qic_res = { + "Quad Interrupt Controller", 0xFC70, 0xFCFF }; + +/* This function is used to pack a data bit stream inside a message. + * It writes num_bits of the data buffer in msg starting at start_bit. + * Note: This function assumes that any unused bit in the data stream + * is set to zero so that the ors will work correctly */ +#define BITS_PER_BYTE 8 +static void +cat_pack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits) +{ + /* compute initial shift needed */ + const __u16 offset = start_bit % BITS_PER_BYTE; + __u16 len = num_bits / BITS_PER_BYTE; + __u16 byte = start_bit / BITS_PER_BYTE; + __u16 residue = (num_bits % BITS_PER_BYTE) + offset; + int i; + + /* adjust if we have more than a byte of residue */ + if(residue >= BITS_PER_BYTE) { + residue -= BITS_PER_BYTE; + len++; + } + + /* clear out the bits. We assume here that if len==0 then + * residue >= offset. This is always true for the catbus + * operations */ + msg[byte] &= 0xff << (BITS_PER_BYTE - offset); + msg[byte++] |= data[0] >> offset; + if(len == 0) + return; + for(i = 1; i < len; i++) + msg[byte++] = (data[i-1] << (BITS_PER_BYTE - offset)) + | (data[i] >> offset); + if(residue != 0) { + __u8 mask = 0xff >> residue; + __u8 last_byte = data[i-1] << (BITS_PER_BYTE - offset) + | (data[i] >> offset); + + last_byte &= ~mask; + msg[byte] &= mask; + msg[byte] |= last_byte; + } + return; +} +/* unpack the data again (same arguments as cat_pack()). data buffer + * must be zero populated. + * + * Function: given a message string move to start_bit and copy num_bits into + * data (starting at bit 0 in data). + */ +static void +cat_unpack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits) +{ + /* compute initial shift needed */ + const __u16 offset = start_bit % BITS_PER_BYTE; + __u16 len = num_bits / BITS_PER_BYTE; + const __u8 last_bits = num_bits % BITS_PER_BYTE; + __u16 byte = start_bit / BITS_PER_BYTE; + int i; + + if(last_bits != 0) + len++; + + /* special case: want < 8 bits from msg and we can get it from + * a single byte of the msg */ + if(len == 0 && BITS_PER_BYTE - offset >= num_bits) { + data[0] = msg[byte] << offset; + data[0] &= 0xff >> (BITS_PER_BYTE - num_bits); + return; + } + for(i = 0; i < len; i++) { + /* this annoying if has to be done just in case a read of + * msg one beyond the array causes a panic */ + if(offset != 0) { + data[i] = msg[byte++] << offset; + data[i] |= msg[byte] >> (BITS_PER_BYTE - offset); + } + else { + data[i] = msg[byte++]; + } + } + /* do we need to truncate the final byte */ + if(last_bits != 0) { + data[i-1] &= 0xff << (BITS_PER_BYTE - last_bits); + } + return; +} + +static void +cat_build_header(__u8 *header, const __u16 len, const __u16 smallest_reg_bits, + const __u16 longest_reg_bits) +{ + int i; + __u16 start_bit = (smallest_reg_bits - 1) % BITS_PER_BYTE; + __u8 *last_byte = &header[len - 1]; + + if(start_bit == 0) + start_bit = 1; /* must have at least one bit in the hdr */ + + for(i=0; i < len; i++) + header[i] = 0; + + for(i = start_bit; i > 0; i--) + *last_byte = ((*last_byte) << 1) + 1; + +} + +static int +cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 op) +{ + __u8 parity, inst, inst_buf[4] = { 0 }; + __u8 iseq[VOYAGER_MAX_SCAN_PATH], hseq[VOYAGER_MAX_REG_SIZE]; + __u16 ibytes, hbytes, padbits; + int i; + + /* + * Parity is the parity of the register number + 1 (READ_REGISTER + * and WRITE_REGISTER always add '1' to the number of bits == 1) + */ + parity = (__u8)(1 + (reg & 0x01) + + ((__u8)(reg & 0x02) >> 1) + + ((__u8)(reg & 0x04) >> 2) + + ((__u8)(reg & 0x08) >> 3)) % 2; + + inst = ((parity << 7) | (reg << 2) | op); + + outb(VOYAGER_CAT_IRCYC, CAT_CMD); + if(!modp->scan_path_connected) { + if(asicp->asic_id != VOYAGER_CAT_ID) { + printk("**WARNING***: cat_sendinst has disconnected scan path not to CAT asic\n"); + return 1; + } + outb(VOYAGER_CAT_HEADER, CAT_DATA); + outb(inst, CAT_DATA); + if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) { + CDEBUG(("VOYAGER CAT: cat_sendinst failed to get CAT_HEADER\n")); + return 1; + } + return 0; + } + ibytes = modp->inst_bits / BITS_PER_BYTE; + if((padbits = modp->inst_bits % BITS_PER_BYTE) != 0) { + padbits = BITS_PER_BYTE - padbits; + ibytes++; + } + hbytes = modp->largest_reg / BITS_PER_BYTE; + if(modp->largest_reg % BITS_PER_BYTE) + hbytes++; + CDEBUG(("cat_sendinst: ibytes=%d, hbytes=%d\n", ibytes, hbytes)); + /* initialise the instruction sequence to 0xff */ + for(i=0; i < ibytes + hbytes; i++) + iseq[i] = 0xff; + cat_build_header(hseq, hbytes, modp->smallest_reg, modp->largest_reg); + cat_pack(iseq, modp->inst_bits, hseq, hbytes * BITS_PER_BYTE); + inst_buf[0] = inst; + inst_buf[1] = 0xFF >> (modp->largest_reg % BITS_PER_BYTE); + cat_pack(iseq, asicp->bit_location, inst_buf, asicp->ireg_length); +#ifdef VOYAGER_CAT_DEBUG + printk("ins = 0x%x, iseq: ", inst); + for(i=0; i< ibytes + hbytes; i++) + printk("0x%x ", iseq[i]); + printk("\n"); +#endif + if(cat_shiftout(iseq, ibytes, hbytes, padbits)) { + CDEBUG(("VOYAGER CAT: cat_sendinst: cat_shiftout failed\n")); + return 1; + } + CDEBUG(("CAT SHIFTOUT DONE\n")); + return 0; +} + +static int +cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, + __u8 *value) +{ + if(!modp->scan_path_connected) { + if(asicp->asic_id != VOYAGER_CAT_ID) { + CDEBUG(("VOYAGER CAT: ERROR: cat_getdata to CAT asic with scan path connected\n")); + return 1; + } + if(reg > VOYAGER_SUBADDRHI) + outb(VOYAGER_CAT_RUN, CAT_CMD); + outb(VOYAGER_CAT_DRCYC, CAT_CMD); + outb(VOYAGER_CAT_HEADER, CAT_DATA); + *value = inb(CAT_DATA); + outb(0xAA, CAT_DATA); + if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) { + CDEBUG(("cat_getdata: failed to get VOYAGER_CAT_HEADER\n")); + return 1; + } + return 0; + } + else { + __u16 sbits = modp->num_asics -1 + asicp->ireg_length; + __u16 sbytes = sbits / BITS_PER_BYTE; + __u16 tbytes; + __u8 string[VOYAGER_MAX_SCAN_PATH], trailer[VOYAGER_MAX_REG_SIZE]; + __u8 padbits; + int i; + + outb(VOYAGER_CAT_DRCYC, CAT_CMD); + + if((padbits = sbits % BITS_PER_BYTE) != 0) { + padbits = BITS_PER_BYTE - padbits; + sbytes++; + } + tbytes = asicp->ireg_length / BITS_PER_BYTE; + if(asicp->ireg_length % BITS_PER_BYTE) + tbytes++; + CDEBUG(("cat_getdata: tbytes = %d, sbytes = %d, padbits = %d\n", + tbytes, sbytes, padbits)); + cat_build_header(trailer, tbytes, 1, asicp->ireg_length); + + + for(i = tbytes - 1; i >= 0; i--) { + outb(trailer[i], CAT_DATA); + string[sbytes + i] = inb(CAT_DATA); + } + + for(i = sbytes - 1; i >= 0; i--) { + outb(0xaa, CAT_DATA); + string[i] = inb(CAT_DATA); + } + *value = 0; + cat_unpack(string, padbits + (tbytes * BITS_PER_BYTE) + asicp->asic_location, value, asicp->ireg_length); +#ifdef VOYAGER_CAT_DEBUG + printk("value=0x%x, string: ", *value); + for(i=0; i< tbytes+sbytes; i++) + printk("0x%x ", string[i]); + printk("\n"); +#endif + + /* sanity check the rest of the return */ + for(i=0; i < tbytes; i++) { + __u8 input = 0; + + cat_unpack(string, padbits + (i * BITS_PER_BYTE), &input, BITS_PER_BYTE); + if(trailer[i] != input) { + CDEBUG(("cat_getdata: failed to sanity check rest of ret(%d) 0x%x != 0x%x\n", i, input, trailer[i])); + return 1; + } + } + CDEBUG(("cat_getdata DONE\n")); + return 0; + } +} + +static int +cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, __u8 pad_bits) +{ + int i; + + for(i = data_bytes + header_bytes - 1; i >= header_bytes; i--) + outb(data[i], CAT_DATA); + + for(i = header_bytes - 1; i >= 0; i--) { + __u8 header = 0; + __u8 input; + + outb(data[i], CAT_DATA); + input = inb(CAT_DATA); + CDEBUG(("cat_shiftout: returned 0x%x\n", input)); + cat_unpack(data, ((data_bytes + i) * BITS_PER_BYTE) - pad_bits, + &header, BITS_PER_BYTE); + if(input != header) { + CDEBUG(("VOYAGER CAT: cat_shiftout failed to return header 0x%x != 0x%x\n", input, header)); + return 1; + } + } + return 0; +} + +static int +cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp, + __u8 reg, __u8 value) +{ + outb(VOYAGER_CAT_DRCYC, CAT_CMD); + if(!modp->scan_path_connected) { + if(asicp->asic_id != VOYAGER_CAT_ID) { + CDEBUG(("VOYAGER CAT: ERROR: scan path disconnected when asic != CAT\n")); + return 1; + } + outb(VOYAGER_CAT_HEADER, CAT_DATA); + outb(value, CAT_DATA); + if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) { + CDEBUG(("cat_senddata: failed to get correct header response to sent data\n")); + return 1; + } + if(reg > VOYAGER_SUBADDRHI) { + outb(VOYAGER_CAT_RUN, CAT_CMD); + outb(VOYAGER_CAT_END, CAT_CMD); + outb(VOYAGER_CAT_RUN, CAT_CMD); + } + + return 0; + } + else { + __u16 hbytes = asicp->ireg_length / BITS_PER_BYTE; + __u16 dbytes = (modp->num_asics - 1 + asicp->ireg_length)/BITS_PER_BYTE; + __u8 padbits, dseq[VOYAGER_MAX_SCAN_PATH], + hseq[VOYAGER_MAX_REG_SIZE]; + int i; + + if((padbits = (modp->num_asics - 1 + + asicp->ireg_length) % BITS_PER_BYTE) != 0) { + padbits = BITS_PER_BYTE - padbits; + dbytes++; + } + if(asicp->ireg_length % BITS_PER_BYTE) + hbytes++; + + cat_build_header(hseq, hbytes, 1, asicp->ireg_length); + + for(i = 0; i < dbytes + hbytes; i++) + dseq[i] = 0xff; + CDEBUG(("cat_senddata: dbytes=%d, hbytes=%d, padbits=%d\n", + dbytes, hbytes, padbits)); + cat_pack(dseq, modp->num_asics - 1 + asicp->ireg_length, + hseq, hbytes * BITS_PER_BYTE); + cat_pack(dseq, asicp->asic_location, &value, + asicp->ireg_length); +#ifdef VOYAGER_CAT_DEBUG + printk("dseq "); + for(i=0; i 1) { + /* set auto increment */ + __u8 newval; + + if(cat_read(modp, asicp, VOYAGER_AUTO_INC_REG, &val)) { + CDEBUG(("cat_subaddrsetup: read of VOYAGER_AUTO_INC_REG failed\n")); + return 1; + } + CDEBUG(("cat_subaddrsetup: VOYAGER_AUTO_INC_REG = 0x%x\n", val)); + newval = val | VOYAGER_AUTO_INC; + if(newval != val) { + if(cat_write(modp, asicp, VOYAGER_AUTO_INC_REG, val)) { + CDEBUG(("cat_subaddrsetup: write to VOYAGER_AUTO_INC_REG failed\n")); + return 1; + } + } + } + if(cat_write(modp, asicp, VOYAGER_SUBADDRLO, (__u8)(offset &0xff))) { + CDEBUG(("cat_subaddrsetup: write to SUBADDRLO failed\n")); + return 1; + } + if(asicp->subaddr > VOYAGER_SUBADDR_LO) { + if(cat_write(modp, asicp, VOYAGER_SUBADDRHI, (__u8)(offset >> 8))) { + CDEBUG(("cat_subaddrsetup: write to SUBADDRHI failed\n")); + return 1; + } + cat_read(modp, asicp, VOYAGER_SUBADDRHI, &val); + CDEBUG(("cat_subaddrsetup: offset = %d, hi = %d\n", offset, val)); + } + cat_read(modp, asicp, VOYAGER_SUBADDRLO, &val); + CDEBUG(("cat_subaddrsetup: offset = %d, lo = %d\n", offset, val)); + return 0; +} + +static int +cat_subwrite(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset, + __u16 len, void *buf) +{ + int i, retval; + + /* FIXME: need special actions for VOYAGER_CAT_ID here */ + if(asicp->asic_id == VOYAGER_CAT_ID) { + CDEBUG(("cat_subwrite: ATTEMPT TO WRITE TO CAT ASIC\n")); + return 1; + } + + if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) { + CDEBUG(("cat_write: cat_subaddrsetup FAILED\n")); + return retval; + } + + if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_WRITE_CONFIG)) { + CDEBUG(("cat_write: cat_sendinst FAILED\n")); + return 1; + } + for(i = 0; i < len; i++) { + if(cat_senddata(modp, asicp, 0xFF, ((__u8 *)buf)[i])) { + CDEBUG(("cat_subwrite: cat_sendata element at %d FAILED\n", i)); + return 1; + } + } + return 0; +} +static int +cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset, + __u16 len, void *buf) +{ + int i, retval; + + if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) { + CDEBUG(("cat_read: cat_subaddrsetup FAILED\n")); + return retval; + } + + if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_READ_CONFIG)) { + CDEBUG(("cat_subread: cat_sendinst failed\n")); + return 1; + } + for(i = 0; i < len; i++) { + if(cat_getdata(modp, asicp, 0xFF, + &((__u8 *)buf)[i])) { + CDEBUG(("cat_subread: cat_getdata element %d failed\n", i)); + return 1; + } + } + return 0; +} + + +/* buffer for storing EPROM data read in during initialisation */ +static __initdata __u8 eprom_buf[0xFFFF]; +static voyager_module_t *voyager_initial_module; + +void +voyager_cat_init(void) +{ + voyager_module_t **modpp = &voyager_initial_module; + voyager_asic_t **asicpp; + voyager_asic_t *qabc_asic = NULL; + int i, j; + unsigned long qic_addr = 0; + __u8 qabc_data[0x20]; + __u8 num_submodules, val; + voyager_eprom_hdr_t *eprom_hdr = (voyager_eprom_hdr_t *)&eprom_buf[0]; + + /* clear the processor counts */ + voyager_extended_vic_processors = 0; + voyager_quad_processors = 0; + + printk("VOYAGER: beginning CAT bus probe\n"); + /* set up the SuperSet Port Block which tells us where the + * CAT communication port is */ + sspb = inb(VOYAGER_SSPB_RELOCATION_PORT) * 0x100; + VDEBUG(("VOYAGER DEBUG: sspb = 0x%x\n", sspb)); + + for(i = VOYAGER_MIN_MODULE; + i <= VOYAGER_MAX_MODULE; i++) { + __u8 input; + int asic; + __u16 eprom_size; + __u16 sp_offset; + + outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT); + outb(i, VOYAGER_CAT_CONFIG_PORT); + + /* check the presence of the module */ + outb(VOYAGER_CAT_RUN, CAT_CMD); + outb(VOYAGER_CAT_IRCYC, CAT_CMD); + outb(VOYAGER_CAT_HEADER, CAT_DATA); + /* stream series of alternating 1's and 0's to stimulate + * response */ + outb(0xAA, CAT_DATA); + input = inb(CAT_DATA); + outb(VOYAGER_CAT_END, CAT_CMD); + if(input != VOYAGER_CAT_HEADER) { + continue; + } + CDEBUG(("VOYAGER DEBUG: found module id 0x%x, %s\n", i, + cat_module_name(i))); + *modpp = kmalloc(sizeof(voyager_module_t), GFP_KERNEL); /*&voyager_module_storage[cat_count++];*/ + if(*modpp == NULL) { + printk("**WARNING** kmalloc failure in cat_init\n"); + continue; + } + memset(*modpp, 0, sizeof(voyager_module_t)); + /* need temporary asic for cat_subread. It will be + * filled in correctly later */ + (*modpp)->asic = kmalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count];*/ + if((*modpp)->asic == NULL) { + printk("**WARNING** kmalloc failure in cat_init\n"); + continue; + } + memset((*modpp)->asic, 0, sizeof(voyager_asic_t)); + (*modpp)->asic->asic_id = VOYAGER_CAT_ID; + (*modpp)->asic->subaddr = VOYAGER_SUBADDR_HI; + (*modpp)->module_addr = i; + (*modpp)->scan_path_connected = 0; + if(i == 0x1a /* PSI */) { + /* Exception leg for modules with no EEPROM */ + printk("Module \"%s\"\n", cat_module_name(i)); + continue; + } + + CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET)); + outb(VOYAGER_CAT_RUN, CAT_CMD); + cat_disconnect(*modpp, (*modpp)->asic); + if(cat_subread(*modpp, (*modpp)->asic, + VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size), + &eprom_size)) { + printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i); + outb(VOYAGER_CAT_END, CAT_CMD); + continue; + } + if(eprom_size > sizeof(eprom_buf)) { + printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size); + outb(VOYAGER_CAT_END, CAT_CMD); + continue; + } + outb(VOYAGER_CAT_END, CAT_CMD); + outb(VOYAGER_CAT_RUN, CAT_CMD); + CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size)); + if(cat_subread(*modpp, (*modpp)->asic, 0, + eprom_size, eprom_buf)) { + outb(VOYAGER_CAT_END, CAT_CMD); + continue; + } + outb(VOYAGER_CAT_END, CAT_CMD); + printk("Module \"%s\", version 0x%x, tracer 0x%x, asics %d\n", + cat_module_name(i), eprom_hdr->version_id, + *((__u32 *)eprom_hdr->tracer), eprom_hdr->num_asics); + (*modpp)->ee_size = eprom_hdr->ee_size; + (*modpp)->num_asics = eprom_hdr->num_asics; + asicpp = &((*modpp)->asic); + sp_offset = eprom_hdr->scan_path_offset; + /* All we really care about are the Quad cards. We + * identify them because they are in a processor slot + * and have only four asics */ + if((i < 0x10 || (i>=0x14 && i < 0x1c) || i>0x1f)) { + modpp = &((*modpp)->next); + continue; + } + /* Now we know it's in a processor slot, does it have + * a quad baseboard submodule */ + outb(VOYAGER_CAT_RUN, CAT_CMD); + cat_read(*modpp, (*modpp)->asic, VOYAGER_SUBMODPRESENT, + &num_submodules); + /* lowest two bits, active low */ + num_submodules = ~(0xfc | num_submodules); + CDEBUG(("VOYAGER CAT: %d submodules present\n", num_submodules)); + if(num_submodules == 0) { + /* fill in the dyadic extended processors */ + __u8 cpu = i & 0x07; + + printk("Module \"%s\": Dyadic Processor Card\n", + cat_module_name(i)); + voyager_extended_vic_processors |= (1<asic, VOYAGER_SUBMODSELECT, &val); + CDEBUG(("cat_init: SUBMODSELECT value = 0x%x\n", val)); + val = (val & 0x7c) | VOYAGER_QUAD_BASEBOARD; + cat_write(*modpp, (*modpp)->asic, VOYAGER_SUBMODSELECT, val); + + outb(VOYAGER_CAT_END, CAT_CMD); + + + CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET)); + outb(VOYAGER_CAT_RUN, CAT_CMD); + cat_disconnect(*modpp, (*modpp)->asic); + if(cat_subread(*modpp, (*modpp)->asic, + VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size), + &eprom_size)) { + printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i); + outb(VOYAGER_CAT_END, CAT_CMD); + continue; + } + if(eprom_size > sizeof(eprom_buf)) { + printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size); + outb(VOYAGER_CAT_END, CAT_CMD); + continue; + } + outb(VOYAGER_CAT_END, CAT_CMD); + outb(VOYAGER_CAT_RUN, CAT_CMD); + CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size)); + if(cat_subread(*modpp, (*modpp)->asic, 0, + eprom_size, eprom_buf)) { + outb(VOYAGER_CAT_END, CAT_CMD); + continue; + } + outb(VOYAGER_CAT_END, CAT_CMD); + /* Now do everything for the QBB submodule 1 */ + (*modpp)->ee_size = eprom_hdr->ee_size; + (*modpp)->num_asics = eprom_hdr->num_asics; + asicpp = &((*modpp)->asic); + sp_offset = eprom_hdr->scan_path_offset; + /* get rid of the dummy CAT asic and read the real one */ + kfree((*modpp)->asic); + for(asic=0; asic < (*modpp)->num_asics; asic++) { + int j; + voyager_asic_t *asicp = *asicpp + = kmalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count++];*/ + voyager_sp_table_t *sp_table; + voyager_at_t *asic_table; + voyager_jtt_t *jtag_table; + + if(asicp == NULL) { + printk("**WARNING** kmalloc failure in cat_init\n"); + continue; + } + memset(asicp, 0, sizeof(voyager_asic_t)); + asicpp = &(asicp->next); + asicp->asic_location = asic; + sp_table = (voyager_sp_table_t *)(eprom_buf + sp_offset); + asicp->asic_id = sp_table->asic_id; + asic_table = (voyager_at_t *)(eprom_buf + sp_table->asic_data_offset); + for(j=0; j<4; j++) + asicp->jtag_id[j] = asic_table->jtag_id[j]; + jtag_table = (voyager_jtt_t *)(eprom_buf + asic_table->jtag_offset); + asicp->ireg_length = jtag_table->ireg_len; + asicp->bit_location = (*modpp)->inst_bits; + (*modpp)->inst_bits += asicp->ireg_length; + if(asicp->ireg_length > (*modpp)->largest_reg) + (*modpp)->largest_reg = asicp->ireg_length; + if (asicp->ireg_length < (*modpp)->smallest_reg || + (*modpp)->smallest_reg == 0) + (*modpp)->smallest_reg = asicp->ireg_length; + CDEBUG(("asic 0x%x, ireg_length=%d, bit_location=%d\n", + asicp->asic_id, asicp->ireg_length, + asicp->bit_location)); + if(asicp->asic_id == VOYAGER_QUAD_QABC) { + CDEBUG(("VOYAGER CAT: QABC ASIC found\n")); + qabc_asic = asicp; + } + sp_offset += sizeof(voyager_sp_table_t); + } + CDEBUG(("Module inst_bits = %d, largest_reg = %d, smallest_reg=%d\n", + (*modpp)->inst_bits, (*modpp)->largest_reg, + (*modpp)->smallest_reg)); + /* OK, now we have the QUAD ASICs set up, use them. + * we need to: + * + * 1. Find the Memory area for the Quad CPIs. + * 2. Find the Extended VIC processor + * 3. Configure a second extended VIC processor (This + * cannot be done for the 51xx. + * */ + outb(VOYAGER_CAT_RUN, CAT_CMD); + cat_connect(*modpp, (*modpp)->asic); + CDEBUG(("CAT CONNECTED!!\n")); + cat_subread(*modpp, qabc_asic, 0, sizeof(qabc_data), qabc_data); + qic_addr = qabc_data[5] << 8; + qic_addr = (qic_addr | qabc_data[6]) << 8; + qic_addr = (qic_addr | qabc_data[7]) << 8; + printk("Module \"%s\": Quad Processor Card; CPI 0x%lx, SET=0x%x\n", + cat_module_name(i), qic_addr, qabc_data[8]); +#if 0 /* plumbing fails---FIXME */ + if((qabc_data[8] & 0xf0) == 0) { + /* FIXME: 32 way 8 CPU slot monster cannot be + * plumbed this way---need to check for it */ + + printk("Plumbing second Extended Quad Processor\n"); + /* second VIC line hardwired to Quad CPU 1 */ + qabc_data[8] |= 0x20; + cat_subwrite(*modpp, qabc_asic, 8, 1, &qabc_data[8]); +#ifdef VOYAGER_CAT_DEBUG + /* verify plumbing */ + cat_subread(*modpp, qabc_asic, 8, 1, &qabc_data[8]); + if((qabc_data[8] & 0xf0) == 0) { + CDEBUG(("PLUMBING FAILED: 0x%x\n", qabc_data[8])); + } +#endif + } +#endif + + { + struct resource *res = kmalloc(sizeof(struct resource),GFP_KERNEL); + memset(res, 0, sizeof(struct resource)); + res->name = kmalloc(128, GFP_KERNEL); + sprintf((char *)res->name, "Voyager %s Quad CPI", cat_module_name(i)); + res->start = qic_addr; + res->end = qic_addr + 0x3ff; + request_resource(&iomem_resource, res); + } + + qic_addr = (unsigned long)ioremap(qic_addr, 0x400); + + for(j = 0; j < 4; j++) { + __u8 cpu = (i & 0x07) + j*4; + if( (qabc_data[8] & (1<next); + } + *modpp = NULL; + printk("CAT Bus Initialisation finished: extended procs 0x%x, quad procs 0x%x\n", voyager_extended_vic_processors, voyager_quad_processors); + request_resource(&ioport_resource, &vic_res); + if(voyager_quad_processors) + request_resource(&ioport_resource, &qic_res); +} + +int +voyager_cat_readb(__u8 module, __u8 asic, int reg) +{ + return 0; +} + +static int +cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp) +{ + __u8 val; + int err = 0; + + if(!modp->scan_path_connected) + return 0; + if(asicp->asic_id != VOYAGER_CAT_ID) { + CDEBUG(("cat_disconnect: ASIC is not CAT\n")); + return 1; + } + err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val); + if(err) { + CDEBUG(("cat_disconnect: failed to read SCANPATH\n")); + return err; + } + val &= VOYAGER_DISCONNECT_ASIC; + err = cat_write(modp, asicp, VOYAGER_SCANPATH, val); + if(err) { + CDEBUG(("cat_disconnect: failed to write SCANPATH\n")); + return err; + } + outb(VOYAGER_CAT_END, CAT_CMD); + outb(VOYAGER_CAT_RUN, CAT_CMD); + modp->scan_path_connected = 0; + + return 0; +} + +static int +cat_connect(voyager_module_t *modp, voyager_asic_t *asicp) +{ + __u8 val; + int err = 0; + + if(modp->scan_path_connected) + return 0; + if(asicp->asic_id != VOYAGER_CAT_ID) { + CDEBUG(("cat_connect: ASIC is not CAT\n")); + return 1; + } + + err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val); + if(err) { + CDEBUG(("cat_connect: failed to read SCANPATH\n")); + return err; + } + val |= VOYAGER_CONNECT_ASIC; + err = cat_write(modp, asicp, VOYAGER_SCANPATH, val); + if(err) { + CDEBUG(("cat_connect: failed to write SCANPATH\n")); + return err; + } + outb(VOYAGER_CAT_END, CAT_CMD); + outb(VOYAGER_CAT_RUN, CAT_CMD); + modp->scan_path_connected = 1; + + return 0; +} Index: linux/2.4/arch/i386/kernel/voyager_smp.c diff -u /dev/null linux/2.4/arch/i386/kernel/voyager_smp.c:1.1.12.1 --- /dev/null Sat Mar 31 18:39:43 2001 +++ linux/2.4/arch/i386/kernel/voyager_smp.c Sat Mar 31 16:41:02 2001 @@ -0,0 +1,1845 @@ +/* -*- mode: c; c-basic-offset: 8 -*- */ + +/* Copyright (C) 1999,2001 + * + * Author: J.E.J.Bottomley@HansenPartnership.com + * + * linux/arch/i386/kernel/voyager_smp.c + * + * This file provides all the same external entries as smp.c but uses + * the voyager hal to provide the functionality + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* The global kernel spinlock */ +spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED; + +/* TLB state -- visible externally, indexed physically */ +struct tlb_state cpu_tlbstate[NR_CPUS] = {[0 ... NR_CPUS-1] = { &init_mm, 0 }}; + +/* CPU IRQ affinity -- set to all ones initially */ +static unsigned long cpu_irq_affinity[NR_CPUS] = { [0 ... NR_CPUS-1] = ~0UL }; + +/* Set when the idlers are all forked - Set in main.c but not actually + * used by any other parts of the kernel */ +int smp_threads_ready = 0; + +/* per CPU data structure (for /proc/cpuinfo et al), visible externally + * indexed physically */ +struct cpuinfo_x86 cpu_data[NR_CPUS]; + +/* physical ID of the CPU used to boot the system */ +unsigned char boot_cpu_id; + +/* which logical number maps to which CPU */ +volatile int __cpu_logical_map[NR_CPUS]; + +/* which physical CPU maps to which logical number */ +volatile int __cpu_number_map[NR_CPUS]; + +/* The memory line addresses for the Quad CPIs */ +struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS]; + +/* The masks for the Extended VIC processors, filled in by cat_init */ +__u32 voyager_extended_vic_processors = 0; + +/* The mask for the Quad Processors (both extended and non-extended) */ +__u32 voyager_quad_processors = 0; + +/* Total count of live CPUs, used in process.c to display + * the CPU information and in irq.c for the per CPU irq + * activity count. Finally exported by i386_ksyms.c */ +int smp_num_cpus = 1; +static int voyager_extended_cpus = 1; + +/* Have we found an SMP box - used by time.c to do the profiling + interrupt for timeslicing; do not set to 1 until the per CPU timer + interrupt is active */ +int smp_found_config = 0; + +/* Used for the invalidate map that's also checked in the spinlock */ +volatile unsigned long smp_invalidate_needed; + +/* Bitmask of currently online CPUs - used by setup.c for + /proc/cpuinfo, visible externally but still physical */ +unsigned long cpu_online_map = 0; + +/* Bitmask of CPUs present in the system - exported by i386_syms.c, used + * by scheduler but indexed physically */ +unsigned long cpu_present_map = 0; + +/* estimate of time used to flush the SMP-local cache - used in + * processor affinity calculations */ +cycles_t cacheflush_time = 0; + +/* The internal functions */ +static void send_CPI(__u32 cpuset, __u8 cpi); +static void ack_CPI(__u8 cpi); +static int ack_QIC_CPI(__u8 cpi); +static void ack_VIC_CPI(__u8 cpi); +static void send_CPI_allbutself(__u8 cpi); +static void enable_vic_irq(unsigned int irq); +static void disable_vic_irq(unsigned int irq); +static unsigned int startup_vic_irq(unsigned int irq); +static void enable_local_vic_irq(unsigned int irq); +static void disable_local_vic_irq(unsigned int irq); +static void before_handle_vic_irq(unsigned int irq); +static void after_handle_vic_irq(unsigned int irq); +static void set_vic_irq_affinity(unsigned int irq, unsigned long mask); +static void ack_vic_irq(unsigned int irq); +static void vic_enable_cpi(void); +static void do_boot_cpu(__u8 cpuid); +static void do_quad_bootstrap(void); + +int hard_smp_processor_id(void); + +/* Inline functions */ +static inline void +send_one_QIC_CPI(__u8 cpu, __u8 cpi) +{ + voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi = + (smp_processor_id() << 16) + cpi; +} + +static inline void +send_QIC_CPI(__u32 cpuset, __u8 cpi) +{ + int i; + + for(i=0; i>3 &0x7 on the 32 way */ + if(((cpuid >> 2) & 0x03) == i) + /* don't lower our own mask! */ + continue; + + /* masquerade as local Quad CPU */ + outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID); + /* enable the startup CPI */ + outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1); + /* restore cpu id */ + outb(0, QIC_PROCESSOR_ID); + } + __restore_flags(flags); + } +} + + +/* Set up all the basic stuff: read the SMP config and make all the + * SMP information reflect only the boot cpu. All others will be + * brought on-line later. */ +void __init +find_smp_config(void) +{ + boot_cpu_id = hard_smp_processor_id(); + + printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id); + /* The boot CPU must be extended */ + voyager_extended_vic_processors = 1<pte_quick = 0; + c->pmd_quick = 0; + c->pgd_quick = 0; + c->pgtable_cache_sz = 0; + identify_cpu(c); +} + +/* set up the trampoline and return the physical address of the code */ +static __u32 __init +setup_trampoline(void) +{ + /* these two are global symbols in trampoline.S */ + extern __u8 trampoline_end[]; + extern __u8 trampoline_data[]; + + memcpy((__u8 *)trampoline_base, trampoline_data, + trampoline_end - trampoline_data); + return virt_to_phys((__u8 *)trampoline_base); +} + +/* Routine initially called when a non-boot CPU is brought online */ +int __init +start_secondary(void *unused) +{ + __u8 cpuid = hard_smp_processor_id(); + /* external functions not defined in the headers */ + extern void calibrate_delay(void); + extern int cpu_idle(void); + + cpu_init(); + + /* OK, we're in the routine */ + ack_CPI(VIC_CPU_BOOT_CPI); + + /* setup the 8259 master slave pair belonging to this CPU --- + * we won't actually receive any until the boot CPU + * relinquishes it's static routing mask */ + vic_setup_pic(); + + qic_setup(); + + if(is_cpu_quad() && !is_cpu_extended()) { + /* clear the boot CPI */ + __u8 dummy; + + dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi; + printk("read dummy %d\n", dummy); + } + + /* lower the mask to receive CPIs */ + vic_enable_cpi(); + + VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid)); + + /* enable interrupts */ + sti(); + + /* get our bogomips */ + calibrate_delay(); + + /* save our processor parameters */ + smp_store_cpu_info(cpuid); + + /* if we're a quad, we may need to bootstrap other CPUs */ + do_quad_bootstrap(); + + VDEBUG(("VOYAGER DEBUG LOGICAL CPU%d, PHYS CPU%d: set cpu_booted_map going into spin\n", + __cpu_number_map[cpuid], __cpu_logical_map[cpucount])); + + /* signal that we're done */ + cpu_booted_map = 1; + + while(!atomic_read(&smp_commenced)) + rep_nop(); + + local_flush_tlb(); + + return cpu_idle(); +} + +static int __init +fork_by_hand(void) +{ + struct pt_regs regs; + /* don't care about the eip and regs settings since we'll + * never reschedule the forked task. */ + return do_fork(CLONE_VM|CLONE_PID, 0, ®s, 0); +} + + +/* Routine to kick start the given CPU and wait for it to report ready + * (or timeout in startup). When this routine returns, the requested + * CPU is either fully running and configured or known to be dead. + * + * We call this routine sequentially 1 CPU at a time, so no need for + * locking */ + +static void __init +do_boot_cpu(__u8 cpu) +{ + struct task_struct *idle; + int timeout; + unsigned long flags; + int quad_boot = (1<> 4) & 0xFFFF; + + cpucount++; + if(fork_by_hand() < 0) + panic("failed fork for CPU%d", cpu); + + idle = init_task.prev_task; + if (!idle) + panic("No idle process for CPU %d", cpu); + idle->processor = cpu; + __cpu_logical_map[cpucount] = cpu; + __cpu_number_map[cpu] = cpucount; + idle->has_cpu = 1; /* we schedule the first task manually */ + idle->thread.eip = (unsigned long) start_secondary; + del_from_runqueue(idle); + unhash_process(idle); + /* init_tasks (in sched.c) is indexed logically */ + init_tasks[cpucount] = idle; + stack_start.esp = (1024 + PAGE_SIZE + (__u8 *)idle); + /* Note: Don't modify initial ss override */ + VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu, + (unsigned long)hijack_source.val, hijack_source.idt.Segment, + hijack_source.idt.Offset, stack_start.esp)); + /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently + * (so that the booting CPU can find start_32 */ + orig_swapper_pg_dir0 = swapper_pg_dir[0]; +#ifdef CONFIG_M486 + if(page_table_copies == NULL) + panic("No free memory for 486 page tables\n"); + for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++) + page_table_copies[i] = (i * PAGE_SIZE) + | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; + + ((unsigned long *)swapper_pg_dir)[0] = + ((virt_to_phys(page_table_copies)) & PAGE_MASK) + | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; +#else + ((unsigned long *)swapper_pg_dir)[0] = 0x102007; +#endif + + if(quad_boot) { + printk("CPU %d: non extended Quad boot\n", cpu); + hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4); + *hijack_vector = hijack_source.val; + } else { + printk("CPU%d: extended VIC boot\n", cpu); + hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4); + *hijack_vector = hijack_source.val; + /* VIC errata, may also receive interrupt at this address */ + hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4); + *hijack_vector = hijack_source.val; + } + /* All non-boot CPUs start with interrupts fully masked. Need + * to lower the mask of the CPI we're about to send. We do + * this in the VIC by masquerading as the processor we're + * about to boot and lowering its interrupt mask */ + __save_flags(flags); + __cli(); + if(quad_boot) { + send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI); + } else { + outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID); + /* here we're altering registers belonging to `cpu' */ + + outb(VIC_BOOT_INTERRUPT_MASK, 0x21); + /* now go back to our original identity */ + outb(boot_cpu_id, VIC_PROCESSOR_ID); + + /* and boot the CPU */ + + send_CPI((1<processor = boot_cpu_id; + for(i=0; ithread; + + /* + * We don't actually need to load the full TSS, + * basically just the stack pointer and the eip. + */ + + asm volatile( + "movl %0,%%esp\n\t" + "jmp *%1" + : + :"r" (p->esp),"r" (p->eip)); +} + +/* handle a Voyager SYS_INT -- If we don't, the base board will + * panic the system. + * + * System interrupts occur because some problem was detected on the + * various busses. To find out what you have to probe all the + * hardware via the CAT bus. FIXME: At the moment we do nothing. */ +asmlinkage void +smp_vic_sys_interrupt(void) +{ + ack_CPI(VIC_SYS_INT); + printk("Voyager SYSTEM INTERRUPT\n"); +} + +/* Handle a voyager CMN_INT; These interrupts occur either because of + * a system status change or because a single bit memory error + * occurred. FIXME: At the moment, ignore all this. */ +asmlinkage void +smp_vic_cmn_interrupt(void) +{ + ack_CPI(VIC_CMN_INT); + printk("Voyager COMMON INTERRUPT\n"); +} + +/* + * Reschedule call back. Nothing to do, all the work is done + * automatically when we return from the interrupt. */ +asmlinkage void +smp_reschedule_interrupt(void) +{ + /* do nothing */ +} + +static struct mm_struct * flush_mm; +static unsigned long flush_va; +static spinlock_t tlbstate_lock = SPIN_LOCK_UNLOCKED; +#define FLUSH_ALL 0xffffffff + +/* + * We cannot call mmdrop() because we are in interrupt context, + * instead update mm->cpu_vm_mask. + */ +static void inline +leave_mm (unsigned long cpu) +{ + if (cpu_tlbstate[cpu].state == TLBSTATE_OK) + BUG(); + clear_bit(cpu, &cpu_tlbstate[cpu].active_mm->cpu_vm_mask); +} + + +/* + * Invalidate call-back + */ +asmlinkage void +smp_invalidate_interrupt(void) +{ + __u8 cpu = smp_processor_id(); + + if(!test_bit(cpu, &smp_invalidate_needed)) + return; + /* This will flood messages. Don't uncomment unless you see + * Problems with cross cpu invalidation + VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n", + smp_processor_id())); + */ + + if (flush_mm == cpu_tlbstate[cpu].active_mm) { + if (cpu_tlbstate[cpu].state == TLBSTATE_OK) { + if (flush_va == FLUSH_ALL) + local_flush_tlb(); + else + __flush_tlb_one(flush_va); + } else + leave_mm(cpu); + } + clear_bit(cpu, &smp_invalidate_needed); +} + +/* All the new flush operations for 2.4 */ + + +/* This routine is called with a physical cpu mask */ +static void +flush_tlb_others (unsigned long cpumask, struct mm_struct *mm, + unsigned long va) +{ + int stuck = 50000; + + if (!cpumask) + BUG(); + if ((cpumask & cpu_online_map) != cpumask) + BUG(); + if (cpumask & (1 << smp_processor_id())) + BUG(); + if (!mm) + BUG(); + + spin_lock(&tlbstate_lock); + + flush_mm = mm; + flush_va = va; + atomic_set_mask(cpumask, &smp_invalidate_needed); + /* + * We have to send the CPI only to + * CPUs affected. + */ + send_CPI(cpumask, VIC_INVALIDATE_CPI); + + while (smp_invalidate_needed) { + if(--stuck == 0) { + printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id()); + break; + } + } + + /* Uncomment only to debug invalidation problems + VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu)); + */ + + flush_mm = NULL; + flush_va = 0; + spin_unlock(&tlbstate_lock); +} + +void +flush_tlb_current_task(void) +{ + struct mm_struct *mm = current->mm; + unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id()); + + local_flush_tlb(); + if (cpu_mask) + flush_tlb_others(cpu_mask, mm, FLUSH_ALL); +} + + +void +flush_tlb_mm (struct mm_struct * mm) +{ + unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id()); + + if (current->active_mm == mm) { + if (current->mm) + local_flush_tlb(); + else + leave_mm(smp_processor_id()); + } + if (cpu_mask) + flush_tlb_others(cpu_mask, mm, FLUSH_ALL); +} + +void flush_tlb_page(struct vm_area_struct * vma, unsigned long va) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id()); + + if (current->active_mm == mm) { + if(current->mm) + __flush_tlb_one(va); + else + leave_mm(smp_processor_id()); + } + + if (cpu_mask) + flush_tlb_others(cpu_mask, mm, va); +} + +/* enable the requested IRQs */ +asmlinkage void +smp_enable_irq_interrupt(void) +{ + __u8 irq; + __u8 cpu = smp_processor_id(); + + VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu, + vic_irq_enable_mask[cpu])); + + spin_lock(&vic_irq_lock); + for(irq = 0; irq < 16; irq++) { + if(vic_irq_enable_mask[cpu] & (1<func; + void *info = call_data->info; + /* must take copy of wait because call_data may be replaced + * unless the function is waiting for us to finish */ + int wait = call_data->wait; + __u8 cpu = smp_processor_id(); + + /* + * Notify initiating CPU that I've grabbed the data and am + * about to execute the function + */ + if(!test_and_clear_bit(cpu, &call_data->started)) { + /* If the bit wasn't set, this could be a replay */ + printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu); + return; + } + /* + * At this point the info structure may be out of scope unless wait==1 + */ + (*func)(info); + if (wait) + clear_bit(cpu, &call_data->finished); +} + +/* Call this function on all CPUs using the function_interrupt above + The function to run. This must be fast and non-blocking. + An arbitrary pointer to pass to the function. + If true, keep retrying until ready. + If true, wait until function has completed on other CPUs. + [RETURNS] 0 on success, else a negative status code. Does not return until + remote CPUs are nearly ready to execute <> or are or have executed. +*/ +int +smp_call_function (void (*func) (void *info), void *info, int retry, + int wait) +{ + struct call_data_struct data; + __u32 mask = cpu_online_map; + + mask &= ~(1<= 0x93000) + BUG(); +} + +/* send a reschedule CPI to one CPU by physical CPU number*/ +void +smp_send_reschedule(int cpu) +{ + send_one_CPI(cpu, VIC_RESCHEDULE_CPI); +} + + +int +hard_smp_processor_id(void) +{ + __u8 i; + __u8 cpumask = inb(VIC_PROC_WHO_AM_I); + if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER) + return cpumask & 0x1F; + + for(i = 0; i < 8; i++) { + if(cpumask & (1<eip); + + if (--prof_counter[cpu] <= 0) { + /* + * The multiplier may have changed since the last time we got + * to this point as a result of the user writing to + * /proc/profile. In this case we need to adjust the APIC + * timer accordingly. + * + * Interrupts are already masked off at this point. + */ + prof_counter[cpu] = prof_multiplier[cpu]; + if (prof_counter[cpu] != prof_old_multiplier[cpu]) { + /* FIXME: need to update the vic timer tick here */ + prof_old_multiplier[cpu] = prof_counter[cpu]; + } + +#ifdef CONFIG_SMP + update_process_times(user); +#endif + } + if( ((1<1 eligible CPUs are equal lowest, the + * lowest processor number gets it. + * + * The priority of a CPU is controlled by a special per-CPU + * VIC priority register which is 3 bits wide 0 being lowest + * and 7 highest priority.. + * + * Therefore we subtract the average number of interrupts from + * the number we've fielded. If this number is negative, we + * lower the activity count and if it is positive, we raise + * it. + * + * I'm afraid this still leads to odd looking interrupt counts: + * the totals are all roughly equal, but the individual ones + * look rather skewed. + * + * FIXME: This algorithm is total crap when mixed with SMP + * affinity code since we now try to even up the interrupt + * counts when an affinity binding is keeping them on a + * particular CPU*/ + weight = (vic_intr_count[cpu]*voyager_extended_cpus + - vic_intr_total) >> 4; + weight += 4; + if(weight > 7) + weight = 7; + if(weight < 0) + weight = 0; + + outb((__u8)weight, VIC_PRIORITY_REGISTER); + +#ifdef VOYAGER_DEBUG + if((vic_tick[cpu] & 0xFFF) == 0) { + /* print this message roughly every 25 secs */ + printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n", + cpu, vic_tick[cpu], weight); + } +#endif +} + +/* setup the profiling timer */ +int +setup_profiling_timer(unsigned int multiplier) +{ + int i; + + if ( (!multiplier)) + return -EINVAL; + + /* + * Set the new multiplier for each CPU. CPUs don't start using the + * new values until the next timer interrupt in which they do process + * accounting. + */ + for (i = 0; i < NR_CPUS; ++i) + prof_multiplier[i] = multiplier; + + return 0; +} + + +/* initialise the voyager interrupt gates + * + * This uses the macros in irq.h to set up assembly jump gates. The + * calls are then redirected to the same routine with smp_ prefixed */ +BUILD_SMP_INTERRUPT(vic_sys_interrupt, VIC_SYS_INT) +BUILD_SMP_INTERRUPT(vic_cmn_interrupt, VIC_CMN_INT) +BUILD_SMP_TIMER_INTERRUPT(vic_cpi_interrupt, VIC_CPI_LEVEL0); + +/* do all the QIC interrupts */ +BUILD_SMP_TIMER_INTERRUPT(qic_timer_interrupt, QIC_TIMER_CPI); +BUILD_SMP_INTERRUPT(qic_invalidate_interrupt, QIC_INVALIDATE_CPI); +BUILD_SMP_INTERRUPT(qic_reschedule_interrupt, QIC_RESCHEDULE_CPI); +BUILD_SMP_INTERRUPT(qic_enable_irq_interrupt, QIC_ENABLE_IRQ_CPI); +BUILD_SMP_INTERRUPT(qic_call_function_interrupt, QIC_CALL_FUNCTION_CPI); + +/* The CPIs are handled in the per cpu 8259s, so they must be + * enabled to be received: FIX: enabling the CPIs in the early + * boot sequence interferes with bug checking; enable them later + * on in smp_init */ +#define VIC_SET_GATE(cpi, vector) \ + set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector)) +#define QIC_SET_GATE(cpi, vector) \ + set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector)) + +void __init +voyager_smp_intr_init(void) +{ + int i; + + /* initialize the per cpu irq mask to all disabled */ + for(i = 0; i < NR_CPUS; i++) + vic_irq_mask[i] = 0xFFFF; + + VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt); + + VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt); + VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt); + + QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt); + QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt); + QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt); + QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt); + QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt); + + + /* now put the VIC descriptor into the first 48 IRQs + * + * This is for later: first 16 correspond to PC IRQs; next 16 + * are Primary MC IRQs and final 16 are Secondary MC IRQs */ + for(i = 0; i < 48; i++) + irq_desc[i].handler = &vic_irq_type; +} + +/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per + * processor to recieve CPI */ +static void +send_CPI(__u32 cpuset, __u8 cpi) +{ + int i; + __u32 quad_cpuset = (cpuset & voyager_quad_processors); + + if(cpi < VIC_START_FAKE_CPI) { + /* fake CPI are only used for booting, so send to the + * extended quads as well---Quads must be VIC booted */ + outb((__u8)(cpuset), VIC_CPI_Registers[cpi]); + return; + } + if(quad_cpuset) + send_QIC_CPI(quad_cpuset, cpi); + cpuset &= ~quad_cpuset; + cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */ + if(cpuset == 0) + return; + for(i = 0; i < smp_num_cpus; i++) { + __u8 cpu = __cpu_logical_map[i]; + if(cpuset & (1<qic_cpi[cpi].cpi; +} + +/* Acknowledge receipt of CPI in the VIC (essentially an EOI) */ +static void +ack_VIC_CPI(__u8 cpi) +{ +#ifdef VOYAGER_DEBUG + unsigned long flags; + __u16 isr; + __u8 cpu = smp_processor_id(); + + __save_flags(flags); + __cli(); + isr = vic_read_isr(); + if((isr & (1<<(cpi &7))) == 0) { + printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi); + } +#endif + /* send specific EOI; the two system interrupts have + * bit 4 set for a separate vector but behave as the + * corresponding 3 bit intr */ + outb_p(0x60|(cpi & 7),0x20); + +#ifdef VOYAGER_DEBUG + if((vic_read_isr() & (1<<(cpi &7))) != 0) { + printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi); + } + __restore_flags(flags); +#endif +} + +/* cribbed with thanks from irq.c */ +#define __byte(x,y) (((unsigned char *)&(y))[x]) +#define cached_21(cpu) (__byte(0,vic_irq_mask[cpu])) +#define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu])) + +static unsigned int +startup_vic_irq(unsigned int irq) +{ + enable_vic_irq(irq); + + return 0; +} + +/* The enable and disable routines. This is where we run into + * conflicting architectural philosophy. Fundamentally, the voyager + * architecture does not expect to have to disable interrupts globally + * (the IRQ controllers belong to each CPU). The processor masquerade + * which is used to start the system shouldn't be used in a running OS + * since it will cause great confusion if two separate CPUs drive to + * the same IRQ controller (I know, I've tried it). + * + * The solution is a variant on the NCR lazy SPL design: + * + * 1) To disable an interrupt, do nothing (other than set the + * IRQ_DISABLED flag). This dares the interrupt actually to arrive. + * + * 2) If the interrupt dares to come in, raise the local mask against + * it (this will result in all the CPU masks being raised + * eventually). + * + * 3) To enable the interrupt, lower the mask on the local CPU and + * broadcast an Interrupt enable CPI which causes all other CPUs to + * adjust their masks accordingly. */ + +static void +enable_vic_irq(unsigned int irq) +{ + int i; + /* linux doesn't to processor-irq affinity, so enable on + * all CPUs we know about */ + __u8 cpu = smp_processor_id(); + __u16 mask = (1<status |= IRQ_REPLAY | IRQ_INPROGRESS; + } else if(desc->status & IRQ_DISABLED) { + /* Damn, the interrupt actually arrived, do the lazy + * disable thing. The interrupt routine in irq.c will + * not handle a IRQ_DISABLED interrupt, so nothing more + * need be done here */ + VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n", + irq, cpu)); + disable_local_vic_irq(irq); + desc->status |= IRQ_REPLAY; + } else { + desc->status &= ~IRQ_REPLAY; + } + + spin_unlock(&vic_irq_lock); +} + +/* Finish the VIC interrupt: basically mask */ +static void +after_handle_vic_irq(unsigned int irq) +{ + irq_desc_t *desc = irq_desc + irq; + + spin_lock(&vic_irq_lock); + { + unsigned int status = desc->status & ~IRQ_INPROGRESS; +#ifdef VOYAGER_DEBUG + __u16 isr; +#endif + + desc->status = status; + if ((status & IRQ_DISABLED)) + disable_local_vic_irq(irq); +#ifdef VOYAGER_DEBUG + /* DEBUG: before we ack, check what's in progress */ + isr = vic_read_isr(); + if((isr & (1<status &= ~(IRQ_REPLAY | IRQ_INPROGRESS); + } +#ifdef VOYAGER_DEBUG + isr = vic_read_isr(); + if((isr & (1<= 32) + /* You can only have 32 interrupts in a voyager system + * (and 32 only if you have a secondary microchannel + * bus) */ + return; + + for(i = 0; i < smp_num_cpus; i++) { + __u8 cpu = __cpu_logical_map[i]; + unsigned long cpu_mask = (1< +#ifdef CONFIG_VOYAGER +#include +#endif + extern void wakeup_bdflush(int); extern void reset_vc(unsigned int); extern struct list_head super_blocks; @@ -78,6 +82,12 @@ printk("Keyboard mode set to XLATE\n"); } break; +#ifdef CONFIG_VOYAGER + case 'c': + printk("VOYAGER DUMP\n"); + voyager_dump(); + break; +#endif /* CONFIG_VOYAGER */ #ifdef CONFIG_VT case 'k': /* K -- SAK */ printk("SAK\n"); Index: linux/2.4/drivers/scsi/53c7,8xx.c diff -u linux/2.4/drivers/scsi/53c7,8xx.c:1.1.1.6 linux/2.4/drivers/scsi/53c7,8xx.c:1.1.1.6.2.1 --- linux/2.4/drivers/scsi/53c7,8xx.c:1.1.1.6 Sat Mar 31 15:45:45 2001 +++ linux/2.4/drivers/scsi/53c7,8xx.c Sat Mar 31 16:41:02 2001 @@ -236,6 +236,7 @@ #include #include #include +#include #include #include "scsi.h" @@ -268,6 +269,8 @@ static int NCR53c8xx_dsa_len; static void NCR53c7x0_intr(int irq, void *dev_id, struct pt_regs * regs); static void do_NCR53c7x0_intr(int irq, void *dev_id, struct pt_regs * regs); +static void do_q720_intr(int irq, void *dev_id, struct pt_regs * regs); + static int ncr_halt (struct Scsi_Host *host); static void intr_phase_mismatch (struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd); @@ -448,6 +451,8 @@ * and chip numbers. */ +#ifndef CONFIG_MCA + static struct { unsigned short pci_device_id; int chip; @@ -468,9 +473,6 @@ #define NPCI_CHIP_IDS (sizeof (pci_chip_ids) / sizeof(pci_chip_ids[0])) -#define ROUNDUP(adr,type) \ - ((void *) (((long) (adr) + sizeof(type) - 1) & ~(sizeof(type) - 1))) - /* * Forced detection and autoprobe code for various hardware. Currently, * entry points for these are not included in init/main.c because if the @@ -508,6 +510,20 @@ #define OVERRIDE_LIMIT commandline_current #endif +#endif /* CONFIG_MCA */ + +#ifdef CONFIG_MCA +struct q720_table { + int base; + struct q720_table *next; +}; + +static struct q720_table *q720_table = NULL; +#endif /* CONFIG_MCA */ + +#define ROUNDUP(adr,type) \ + ((void *) (((long) (adr) + sizeof(type) - 1) & ~(sizeof(type) - 1))) + /* * Function: issue_to_cmd * @@ -558,6 +574,7 @@ static void internal_setup(int board, int chip, char *str, int *ints) { +#ifndef CONFIG_MCA unsigned char pci; /* Specifies a PCI override, with bus, device, function */ @@ -595,6 +612,7 @@ } else { printk ("53c7,7x0.c:internal_setup() : too many overrides\n"); } +#endif } /* @@ -898,6 +916,18 @@ expected_clock = hostdata->scsi_clock = 40000000; expected_id = 7; break; + case NCR_Q720: + /* this is wide, but not yet supported as such */ + hostdata->dstat_sir_intr = NCR53c8x0_dstat_sir_intr; + hostdata->init_save_regs = NULL; + hostdata->dsa_fixup = NCR53c8xx_dsa_fixup; + hostdata->init_fixup = NCR53c8x0_init_fixup; + hostdata->soft_reset = NCR53c8x0_soft_reset; + hostdata->run_tests = NCR53c8xx_run_tests; +/* Is the SCSI clock ever anything else on these chips? */ + expected_clock = hostdata->scsi_clock = 40000000; + expected_id = 7; + break; default: printk ("scsi%d : chip type of %d is not supported yet, detaching.\n", host->host_no, hostdata->chip); @@ -1029,6 +1059,7 @@ */ if (hostdata->chip / 100 == 8) { expected_ccf = clock_to_ccf (expected_clock); + NCR53c7x0_write8(SCNTL3_REG_800, 0x33); hostdata->saved_scntl3 = NCR53c7x0_read8(SCNTL3_REG_800); ccf = hostdata->saved_scntl3 & SCNTL3_800_CCF_MASK; if (expected_ccf != -1 && ccf != expected_ccf && !ccf) { @@ -1109,11 +1140,13 @@ search->irq == host->irq && search != host); search=search->next); if (!search) { -#ifdef __powerpc__ - if (request_irq(host->irq, do_NCR53c7x0_intr, SA_SHIRQ, "53c7,8xx", NULL)) -#else - if (request_irq(host->irq, do_NCR53c7x0_intr, SA_INTERRUPT, "53c7,8xx", NULL)) + int ret = +#ifdef CONFIG_MCA + (hostdata->chip == NCR_Q720) ? + request_irq(host->irq, do_q720_intr, SA_INTERRUPT, "Q720", NULL) : #endif + request_irq(host->irq, do_NCR53c7x0_intr, SA_INTERRUPT, "53c7,8xx", NULL); + if (ret) { @@ -1138,9 +1171,13 @@ scsi_unregister (host); return -1; } else { - if (host->io_port) { - host->n_io_port = 128; - request_region (host->io_port, host->n_io_port, "ncr53c7,8xx"); + if (host->io_port) { + if(hostdata->chip == NCR_Q720) { + host->n_io_port = 0x80; + } else { + host->n_io_port = 112; + request_region (host->io_port, host->n_io_port, "ncr53c7,8xx"); + } } } @@ -1187,7 +1224,7 @@ switch (chip) { case 825: - case 820: + case NCR_Q720: case 815: case 810: schedule_size = (tpnt->can_queue + 1) * 8 /* JUMP instruction size */; @@ -1208,7 +1245,7 @@ else printk(", dma %d\n", dma); - if ((chip / 100 == 8) && !pci_valid) + if ((chip / 100 == 8) && chip != NCR_Q720) printk ("scsi-ncr53c7,8xx : for better reliability and performance, please use the\n" " PCI override instead.\n" " Syntax : ncr53c8{10,15,20,25}=pci,,,\n" @@ -1293,12 +1330,16 @@ */ if (base) { - instance->base = (unsigned long) base; /* Check for forced I/O mapping */ if (!(options & OPTION_IO_MAPPED)) { options |= OPTION_MEMORY_MAPPED; ok = 1; } + /* + base = ioremap(base, 0x100); + */ + printk("ncr53c7,8xx: remapped ram base to 0x%x\n", base); + instance->base = (unsigned char *) (unsigned long) base; } else { options &= ~OPTION_MEMORY_MAPPED; } @@ -1363,7 +1404,7 @@ return NCR53c7x0_init(instance); } - +#ifndef CONFIG_MCA /* * Function : static int ncr_pci_init(Scsi_Host_Template *tpnt, int board, * int chip, int bus, int device_fn, long long options) @@ -1511,7 +1552,7 @@ return normal_init (tpnt, board, chip, (int) base, io_port, (int) irq, DMA_NONE, 1, bus, device_fn, options); } - +#endif /* CONFIG_MCA */ /* * Function : int NCR53c7xx_detect(Scsi_Host_Template *tpnt) @@ -1529,13 +1570,131 @@ int __init NCR53c7xx_detect(Scsi_Host_Template *tpnt){ int i; + int count = 0; /* Number of boards detected */ +#ifdef CONFIG_MCA + int slot, pos[4]; +#else int current_override; - int count; /* Number of boards detected */ unsigned char pci_bus, pci_device_fn; static short pci_index=0; /* Device index to PCI BIOS calls */ +#endif tpnt->proc_name = "ncr53c7xx"; +#ifdef CONFIG_MCA + if((slot = mca_find_adapter(0x01ba, 0)) != MCA_NOTFOUND) { + int iobase, irq; + unsigned int rambase; + + pos[0] = mca_read_stored_pos(slot, 2); + pos[1] = mca_read_stored_pos(slot, 3); + pos[2] = mca_read_stored_pos(slot, 4); + pos[3] = mca_read_stored_pos(slot, 5); + + iobase = (pos[2] & 0xfd) << 8; + rambase = ((pos[1] & 0xf0) << 9) + 0xC0000; + switch((pos[0] & 0xd0) >> 6) { + case 2: + irq = 11; + break; + case 3: + irq = 14; + break; + default: + printk("D700: Illegal interrupt\n"); + irq = 0; + break; + } + + normal_init(tpnt, BOARD_GENERIC, 70066, rambase + 0x200, + iobase + 0x200, + irq, DMA_NONE, 0, 0, 0, 0); + count ++; + } + else if((slot = mca_find_adapter(0x0720, 0)) != MCA_NOTFOUND) { + int iobase, irq; + unsigned int rambase; + struct q720_table *new_table; + + pos[0] = mca_read_stored_pos(slot, 2); + pos[1] = mca_read_stored_pos(slot, 3); + pos[2] = mca_read_stored_pos(slot, 4); + pos[3] = mca_read_stored_pos(slot, 5); + + iobase = (0xf8 & pos[0]) << 8; + irq = pos[3] &0x0f; + rambase = ((0x7e & pos[2]) << 20); + rambase += (pos[2] & 0x80) ? 0xF8000000 : 0xB8000000; + mca_set_adapter_name(slot, "NCR Q720 SCSI Quad Host Adapter"); + printk(KERN_INFO "NCR Q720 in slot %d\n", slot); + /* set up card register region */ + request_region((u32)iobase, 64, "Q720"); + + /* set up SIOP individual region */ + request_region((u32)(iobase + 0x200), 0x80, "Q720"); + /* reset the entire adapter */ + outb(inb((u32)(iobase + 0xa)) | 0x10, (u32)(iobase + 0xa)); + /* must wait 5us before touching board again */ + udelay(5); + /* enable the adapter */ + outb(inb((u32)(iobase + 2)) | 0x03, (u32)(iobase +2)); + /* enable ram based mapping */ + outb(inb((u32)(iobase +0xa)) | 0x01, (u32)(iobase +0xa)); + /* enable ram - I/O mapping in lower 1k */ + outb(inb((u32)(iobase +0x11)) | 0x20, (u32)(iobase + 0x11)); + for(i = 0; i < 4; i++) { + /* reset the SIOP */ + outb(iobase + 0x200 + 0x80*i + ISTAT_REG_800, ISTAT_10_SRST); + udelay(5); + outb(iobase + 0x200 + 0x80*i + ISTAT_REG_800, 0x00); + /* clear the DMA FIFO */ + outb(inb(iobase + 0x200 + 0x80*i + CTEST3_REG_800) | CTEST3_800_CLF, + iobase + 0x200 + CTEST3_REG_800); + /* clear SCSI FIFO */ + outb(inb(iobase + 0x200 + 0x80*i + STEST3_REG_800) | STEST3_800_CSF, + iobase + 0x200 + STEST3_REG_800); + } + printk(KERN_INFO "Q720: (vers %d) Adapter Specific regs, iobase=0x%x, rambase=0x%x: ", + (inb(iobase + 0x200 + CTEST3_REG_800) & 0xf0) >> 4, + iobase, rambase); + /* + for(i=0; i<16; i++) + printk("0x%2x ", inb((u32)(iobase + i))); + */ + new_table = kmalloc(sizeof(struct q720_table), GFP_ATOMIC); + if(new_table != NULL) { + new_table->base = iobase; + new_table->next = q720_table; + q720_table = new_table; + for(i=0; i<4; i++) { /* 4 SIOPs per card */ + __u8 id0 = inb((__u16)(iobase + 0x270 + 0x80*i)); + /* + int j; + printk("\nQ720: SIOP%d: ", i); + for(j=0; j<4; j++) + printk("0x%2x ", inb((u32)(iobase + j +0x270 + 0x80*i))); + printk("\n"); + */ + if(id0 & 0x20) { + printk(KERN_WARNING "Q720: SIOP%d: No differential support, skipping\n", i); + continue; + } + /* we use 8xx to signal a 720 chip since the 720 registers + * behave like an 8xx and a lot of the register selection is + * done by the chip/100 == 8 selector */ + normal_init(tpnt, BOARD_GENERIC, NCR_Q720, + rambase + 0x200 + 0x80*i, + iobase + 0x200 + 0x80*i, + irq, DMA_NONE, 0, 0, 0, 0); + count++; + } + } else { + printk("Q720: failed to malloc %d bytes for table\n", + sizeof(q720_table)); + } + } + +#else for (current_override = count = 0; current_override < OVERRIDE_LIMIT; ++current_override) { if (overrides[current_override].pci ? @@ -1569,6 +1728,7 @@ pci_bus, pci_device_fn, /* no options */ 0)) ++count; } +#endif return count; } @@ -1657,12 +1817,13 @@ tmp = NCR53c7x0_read8(DMODE_REG_10); tmp &= (DMODE_800_ERL | DMODE_BL_MASK); - if (!(hostdata->options & OPTION_MEMORY_MAPPED)) { + if (!(hostdata->options & OPTION_MEMORY_MAPPED) + && hostdata->chip != NCR_Q720) { base = (u32) host->io_port; memory_to_ncr = tmp|DMODE_800_DIOM; ncr_to_memory = tmp|DMODE_800_SIOM; } else { - base = virt_to_bus((void *)host->base); + base = host->base; /* currently bus physical -- may change */ memory_to_ncr = ncr_to_memory = tmp; } @@ -4186,9 +4347,9 @@ is_8xx_chip = ((unsigned) (hostdata->chip - 800)) < 100; if (is_8xx_chip) { - sstat0_sist0 = NCR53c7x0_read8(SIST0_REG_800); + sstat0_sist0 = NCR53c7x0_read8(SIST0_REG_800) & NCR53c7x0_read8(SIEN0_REG_800); udelay(1); - sist1 = NCR53c7x0_read8(SIST1_REG_800); + sist1 = NCR53c7x0_read8(SIST1_REG_800) & NCR53c7x0_read8(SIEN1_REG_800); } else { sstat0_sist0 = NCR53c7x0_read8(SSTAT0_REG); sist1 = 0; @@ -4360,6 +4521,22 @@ spin_unlock_irqrestore(&io_request_lock, flags); } +#ifdef CONFIG_MCA +static void +do_q720_intr(int irq, void *dev_id, struct pt_regs *regs) { + unsigned long flags; + + if(q720_table == NULL || (inb(q720_table->base +0xd) & 0xf0) == 0xf0) { + /* SIOP0-3 hasn't interrupted */ + return; + } + spin_lock_irqsave(&io_request_lock, flags); + NCR53c7x0_intr(irq, dev_id, regs); + spin_unlock_irqrestore(&io_request_lock, flags); + +} +#endif + /* * Function : static void NCR53c7x0_intr (int irq, void *dev_id, struct pt_regs * regs) * @@ -4530,8 +4707,9 @@ interrupted = 1; hostdata->state = STATE_HALTED; - if (NCR53c7x0_read8 ((hostdata->chip / 100) == 8 ? - SSTAT1_REG : SSTAT2_REG) & SSTAT2_FF_MASK) + if ((NCR53c7x0_read8 ((hostdata->chip / 100) == 8 ? + SSTAT1_REG : SSTAT2_REG) + & SSTAT2_FF_MASK) && istat & ISTAT_SIP) printk ("scsi%d : SCSI FIFO not empty\n", host->host_no); @@ -4549,11 +4727,19 @@ cmd = (struct NCR53c7x0_cmd *) hostdata->curr; } else { dsa = bus_to_virt(NCR53c7x0_read32(DSA_REG)); + if(hostdata->options & OPTION_DEBUG_INTR) { + printk("scsi%d : dsa = 0x%x\n", host->host_no, dsa); + } for (cmd = (struct NCR53c7x0_cmd *) hostdata->running_list; cmd && (dsa + (hostdata->dsa_start / sizeof(u32))) != cmd->dsa; - cmd = (struct NCR53c7x0_cmd *)(cmd->next)); + cmd = (struct NCR53c7x0_cmd *)(cmd->next)) { + if(hostdata->options & OPTION_DEBUG_INTR) { + printk("scsi%d : cmd (0x%x) : dsa 0x%x, pid %lu, id %d, lun %d\n", host->host_no, cmd, cmd->dsa, cmd->cmd->pid, (int) cmd->cmd->target, (int) cmd->cmd->lun); + print_command(cmd->cmd->cmnd); + } + } } if (hostdata->options & OPTION_DEBUG_INTR) { if (cmd) { @@ -4562,7 +4748,8 @@ (int) cmd->cmd->lun); print_command (cmd->cmd->cmnd); } else { - printk("scsi%d : no active command\n", host->host_no); + printk("scsi%d : no active command\n", + host->host_no); } } if (istat & ISTAT_SIP) { @@ -5011,7 +5198,7 @@ printk("scsi%d : %s : unexpected phase %s.\n", host->host_no, where ? where : "unknown location", sbcl_to_phase(sbcl)); - print_lots (host); + /*print_lots (host);*/ /* Fall through to ACTION_ABORT */ case ACTION_ABORT: abort_connected (host); @@ -5078,6 +5265,10 @@ */ if ((hostdata->chip / 100) == 8) { +#ifdef CONFIG_MCA + printk("scsi%d: fault interrupt on MCA\n", host->host_no); + return; +#else save_flags (flags); cli(); tmp = pcibios_read_config_word (hostdata->pci_bus, @@ -5099,6 +5290,7 @@ host->host_no, tmp); retry = NEVER; } +#endif /* CONFIG_MCA */ } #ifndef notyet @@ -5659,8 +5851,8 @@ save_flags(flags); cli(); ncr_halt (host); - print_lots (host); - dump_events (host, 30); + /*print_lots (host);*/ + /*dump_events (host, 30);*/ ncr_scsi_reset (host); for (tmp = nuke_list = return_outstanding_commands (host, 1 /* free */, 0 /* issue */ ); tmp; tmp = (Scsi_Cmnd *) tmp->SCp.buffer) Index: linux/2.4/drivers/scsi/53c7,8xx.h diff -u linux/2.4/drivers/scsi/53c7,8xx.h:1.1.1.4 linux/2.4/drivers/scsi/53c7,8xx.h:1.1.1.4.2.1 --- linux/2.4/drivers/scsi/53c7,8xx.h:1.1.1.4 Sat Mar 31 15:45:45 2001 +++ linux/2.4/drivers/scsi/53c7,8xx.h Sat Mar 31 16:41:03 2001 @@ -1526,5 +1526,10 @@ /* Paranoid people could use panic() here. */ #define FATAL(host) shutdown((host)); +/* Extra defines for the NCR Q720 card */ + +#define NCR_Q720 827 /* default chip id (must be > 800) */ +#define NCR_Q720_DEFAULT_SCNTL3 0x33 + #endif /* NCR53c7x0_C */ #endif /* NCR53c7x0_H */ Index: linux/2.4/drivers/scsi/Config.in diff -u linux/2.4/drivers/scsi/Config.in:1.1.1.6 linux/2.4/drivers/scsi/Config.in:1.1.1.6.2.1 --- linux/2.4/drivers/scsi/Config.in:1.1.1.6 Sat Mar 31 15:45:45 2001 +++ linux/2.4/drivers/scsi/Config.in Sat Mar 31 16:41:03 2001 @@ -114,7 +114,7 @@ fi fi dep_tristate 'NCR53c406a SCSI support' CONFIG_SCSI_NCR53C406A $CONFIG_SCSI -dep_tristate 'NCR53c7,8xx SCSI support' CONFIG_SCSI_NCR53C7xx $CONFIG_SCSI $CONFIG_PCI +dep_tristate 'NCR53c7,8xx SCSI support' CONFIG_SCSI_NCR53C7xx $CONFIG_SCSI if [ "$CONFIG_SCSI_NCR53C7xx" != "n" ]; then bool ' always negotiate synchronous transfers' CONFIG_SCSI_NCR53C7xx_sync bool ' allow FAST-SCSI [10MHz]' CONFIG_SCSI_NCR53C7xx_FAST Index: linux/2.4/include/asm-i386/hw_irq.h diff -u linux/2.4/include/asm-i386/hw_irq.h:1.1.1.3 linux/2.4/include/asm-i386/hw_irq.h:1.1.1.3.2.1 --- linux/2.4/include/asm-i386/hw_irq.h:1.1.1.3 Sat Mar 31 15:44:14 2001 +++ linux/2.4/include/asm-i386/hw_irq.h Sat Mar 31 16:41:03 2001 @@ -210,7 +210,7 @@ atomic_inc((atomic_t *)&prof_buffer[eip]); } -#ifdef CONFIG_SMP /*more of this file should probably be ifdefed SMP */ +#if defined(CONFIG_SMP) && !defined(CONFIG_VOYAGER) /*more of this file should probably be ifdefed SMP */ static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) { if (IO_APIC_IRQ(i)) send_IPI_self(IO_APIC_VECTOR(i)); Index: linux/2.4/include/asm-i386/smp.h diff -u linux/2.4/include/asm-i386/smp.h:1.1.1.1 linux/2.4/include/asm-i386/smp.h:1.1.1.1.22.1 --- linux/2.4/include/asm-i386/smp.h:1.1.1.1 Fri Jul 28 10:42:51 2000 +++ linux/2.4/include/asm-i386/smp.h Sat Mar 31 16:41:03 2001 @@ -6,6 +6,7 @@ */ #ifndef ASSEMBLY #include +#include #include #include #endif @@ -41,7 +42,23 @@ extern void (*mtrr_hook) (void); extern void zap_low_mappings (void); +#ifdef CONFIG_VOYAGER /* + * On voyager, all CPU's are labelled by their VIC ID which is not + * usually sequential, so we need to map from the contiguous (logical) + * list used in the scheduler to the physical list */ +extern volatile int __cpu_logical_map[NR_CPUS], __cpu_number_map[NR_CPUS]; + +extern inline int cpu_logical_map(int cpu) +{ + return __cpu_logical_map[cpu]; +} +extern inline int cpu_number_map(int cpu) +{ + return __cpu_number_map[cpu]; +} +#else +/* * On x86 all CPUs are mapped 1:1 to the APIC space. * This simplifies scheduling and IPI sending and * compresses data structures. @@ -54,6 +71,7 @@ { return cpu; } +#endif /* * Some lowlevel functions might want to know about @@ -77,12 +95,13 @@ #define smp_processor_id() (current->processor) +#ifdef CONFIG_X86_LOCAL_APIC extern __inline int hard_smp_processor_id(void) { /* we don't want to mark this access volatile - bad code generation */ return GET_APIC_ID(*(unsigned long *)(APIC_BASE+APIC_ID)); } - +#endif #endif /* !ASSEMBLY */ #define NO_PROC_ID 0xFF /* No processor magic marker */ Index: linux/2.4/include/asm-i386/vic.h diff -u /dev/null linux/2.4/include/asm-i386/vic.h:1.1.12.1 --- /dev/null Sat Mar 31 18:41:15 2001 +++ linux/2.4/include/asm-i386/vic.h Sat Mar 31 16:41:03 2001 @@ -0,0 +1,82 @@ +/* Copyright (C) 1999,2001 + * + * Author: J.E.J.Bottomley@HansenPartnership.com + * + * Standard include definitions for the NCR Voyager Interrupt Controller */ + +/* The eight CPI vectors. To activate a CPI, you write a bit mask + * corresponding to the processor set to be interrupted into the + * relevant register. That set of CPUs will then be interrupted with + * the CPI */ +static const int VIC_CPI_Registers[] = + {0xFC00, 0xFC01, 0xFC08, 0xFC09, + 0xFC10, 0xFC11, 0xFC18, 0xFC19 }; + +#define VIC_PROC_WHO_AM_I 0xfc29 +# define QUAD_IDENTIFIER 0xC0 +#define QIC_EXTENDED_PROCESSOR_SELECT 0xFC72 +#define VIC_CPI_BASE_REGISTER 0xFC41 +#define VIC_PROCESSOR_ID 0xFC21 +# define VIC_CPU_MASQUERADE_ENABLE 0x8 + +#define VIC_CLAIM_REGISTER_0 0xFC38 +#define VIC_CLAIM_REGISTER_1 0xFC39 +#define VIC_REDIRECT_REGISTER_0 0xFC60 +#define VIC_REDIRECT_REGISTER_1 0xFC61 +#define VIC_PRIORITY_REGISTER 0xFC20 + +#define VIC_PRIMARY_MC_BASE 0xFC48 +#define VIC_SECONDARY_MC_BASE 0xFC49 + +#define QIC_PROCESSOR_ID 0xFC71 +# define QIC_CPUID_ENABLE 0x08 + +#define QIC_VIC_CPI_BASE_REGISTER 0xFC79 +#define QIC_CPI_BASE_REGISTER 0xFC7A + +#define QIC_MASK_REGISTER0 0xFC80 +#define QIC_MASK_REGISTER1 0xFC81 +# define QIC_BOOT_CPI_MASK 0xFE +# define QIC_CPI_ENABLE 0xC1 + +#define QIC_INTERRUPT_CLEAR0 0xFC8A +#define QIC_INTERRUPT_CLEAR1 0xFC8B + +/* this is where we place the CPI vectors */ +#define VIC_DEFAULT_CPI_BASE 0xC0 +/* this is where we place the QIC CPI vectors */ +#define QIC_DEFAULT_CPI_BASE 0xD0 + +/* These define the CPIs we use in linux */ +#define VIC_CPI_LEVEL0 0 +#define VIC_CPI_LEVEL1 1 +/* now the fake CPIs */ +#define VIC_TIMER_CPI 2 +#define VIC_INVALIDATE_CPI 3 +#define VIC_RESCHEDULE_CPI 4 +#define VIC_ENABLE_IRQ_CPI 5 +#define VIC_CALL_FUNCTION_CPI 6 + +/* Now the QIC CPIs: Since we don't need the two initial levels, + * these are 2 less than the VIC CPIs */ +#define QIC_CPI_OFFSET 1 +#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET) +#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET) +#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET) +#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET) +#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET) + +#define VIC_START_FAKE_CPI VIC_TIMER_CPI +#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_CPI + +/* this is the SYS_INT CPI. */ +#define VIC_SYS_INT 8 +#define VIC_CMN_INT 15 + +/* This is the boot CPI for alternate processors. It gets overwritten + * by the above once the system has activated all available processors */ +#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0 +#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8) +#define VIC_BOOT_INTERRUPT_MASK 0xfe + +extern void smp_vic_timer_interrupt(struct pt_regs *regs); Index: linux/2.4/include/asm-i386/voyager.h diff -u /dev/null linux/2.4/include/asm-i386/voyager.h:1.1.12.1 --- /dev/null Sat Mar 31 18:41:15 2001 +++ linux/2.4/include/asm-i386/voyager.h Sat Mar 31 16:41:03 2001 @@ -0,0 +1,375 @@ +/* Copyright (C) 1999,2001 + * + * Author: J.E.J.Bottomley@HansenPartnership.com + * + * Standard include definitions for the NCR Voyager system */ + +#undef VOYAGER_DEBUG +#undef VOYAGER_CAT_DEBUG + +#ifdef VOYAGER_DEBUG +#define VDEBUG(x) printk x +#else +#define VDEBUG(x) +#endif + +/* There are three levels of voyager machine: 3,4 and 5. The rule is + * if it's less than 3435 it's a Level 3 except for a 3360 which is + * a level 4. A 3435 or above is a Level 5 */ +#define VOYAGER_LEVEL5_AND_ABOVE 0x3435 +#define VOYAGER_LEVEL4 0x3360 + +/* voyager ports in standard I/O space */ +#define VOYAGER_MC_SETUP 0x96 + + +#define VOYAGER_CAT_CONFIG_PORT 0x97 +# define VOYAGER_CAT_DESELECT 0xff +#define VOYAGER_SSPB_RELOCATION_PORT 0x98 + +/* Valid CAT controller commands */ +/* start instruction register cycle */ +#define VOYAGER_CAT_IRCYC 0x01 +/* start data register cycle */ +#define VOYAGER_CAT_DRCYC 0x02 +/* move to execute state */ +#define VOYAGER_CAT_RUN 0x0F +/* end operation */ +#define VOYAGER_CAT_END 0x80 +/* hold in idle state */ +#define VOYAGER_CAT_HOLD 0x90 +/* single step an "intest" vector */ +#define VOYAGER_CAT_STEP 0xE0 +/* return cat controller to CLEMSON mode */ +#define VOYAGER_CAT_CLEMSON 0xFF + +/* the default cat command header */ +#define VOYAGER_CAT_HEADER 0x7F + +/* the range of possible CAT module ids in the system */ +#define VOYAGER_MIN_MODULE 0x10 +#define VOYAGER_MAX_MODULE 0x1f + +/* The voyager registers per asic */ +#define VOYAGER_ASIC_ID_REG 0x00 +#define VOYAGER_ASIC_TYPE_REG 0x01 +/* the sub address registers can be made auto incrementing on reads */ +#define VOYAGER_AUTO_INC_REG 0x02 +# define VOYAGER_AUTO_INC 0x04 +# define VOYAGER_NO_AUTO_INC 0xfb +#define VOYAGER_SUBADDRDATA 0x03 +#define VOYAGER_SCANPATH 0x05 +# define VOYAGER_CONNECT_ASIC 0x01 +# define VOYAGER_DISCONNECT_ASIC 0xfe +#define VOYAGER_SUBADDRLO 0x06 +#define VOYAGER_SUBADDRHI 0x07 +#define VOYAGER_SUBMODSELECT 0x08 +#define VOYAGER_SUBMODPRESENT 0x09 + +#define VOYAGER_SUBADDR_LO 0xff +#define VOYAGER_SUBADDR_HI 0xffff + +/* the maximum size of a scan path -- used to form instructions */ +#define VOYAGER_MAX_SCAN_PATH 0x100 +/* the biggest possible register size (in bytes) */ +#define VOYAGER_MAX_REG_SIZE 4 + +/* Total number of possible modules (including submodules) */ +#define VOYAGER_MAX_MODULES 16 +/* Largest number of asics per module */ +#define VOYAGER_MAX_ASICS_PER_MODULE 7 + +/* the CAT asic of each module is always the first one */ +#define VOYAGER_CAT_ID 0 + +/* voyager instruction operations and registers */ +#define VOYAGER_READ_CONFIG 0x1 +#define VOYAGER_WRITE_CONFIG 0x2 +#define VOYAGER_BYPASS 0xff + +typedef struct voyager_asic +{ + __u8 asic_addr; /*