Voyager Level 5 Architecture

The Logical Architecture is shown below:
 

This can also be downloaded as an xfig file.

The heart of the system is the VIC (Voyager Interrupt Controller) which routes interrupts from the peripherals and the microchannel busses to the processors.  The VIC consists of eight interrupt distribution lines which are connected to up to eight 8259 dyads on the processors.  The VIC interrupt routing algorithms assign a priority to each line, and route to the processor with the highest priority who's interrupt line is not disabled.  The VIC logic sees interrupt disabling in the local 8259 dyad, but not in the processor, so if a processor disables interrupts, the VIC interrupt will still remain pending.  The VIC also supports eight CPIs (Cross Processor Interrupts) which are sent via base board registers and delivered via the 8259 dyad (each CPI is mapped to the low 8 IRQ lines).  This has the unfortunate effect that if one of the low 8 IRQ lines is disabled in the 8259 dyad, the corresponding CPI remains pending until the interrupt mask is lowered.

The system boots and looks like a standard MCA based PC until the processors are brought on-line and the VIC enabled.

The backplane arbitration logic determines which system bus (A or B) information transfers over and thus the voyager architecture can cope with two simultaneous backplane transfers with no throughput degredation.

The CAT (Configuration And Test) controller is used to monitor all aspects of the system.  The system itself is also self monitoring and will deliver a System Interrupt (special global CPI) if anything fails.  The CAT bus is a serial network bus which is connected to almost every component in the system.

Physically, the processor and memory cards are plugged into the system backplane.  Each processor slot contains two VIC IRQ lines, so each processor card can support up to two CPUs.

Depending on the system type, the secondary microchannel bus may not be present.  The secondary microchannel interrupts can be vectored either to the lower 16 IRQs or to a separate set of vectors.  However, the interrupts have only a single mask in the 8259 dyad.
 

32 Way System

After the inception of the voyager architecture (in about 1990), 8 way was considered good enough (very few people even had SMP systems then).  However, as time passed it was perceived as being too limiting.  The first modification came with the Quad CPU card designed to plug into a backplane slot.  Since now there are only two VIC lines for four processors, only two of the four processors can handle interrupts and further, the CPIs cannot be delivered via the 8259 dyads.  On the Quad cards, CPIs are delivered via a cache line invalidation mechanism rather than via the 8259 dyad.  Essentially, to send a CPI to a particular CPU you just write to a special memory area.  The cache line invalidation will be translated into a CPI for the required processor.

The above will go up to 16 way now.  To get to 32 way, a special architecture modification was introduced in the 5100 series of computers.  Insted of having 2 VIC lines per backplane slot this machine has only one, allowing up to 8 CPU slots and thus up to 32 processors.