This BitKeeper patch contains the following changesets: jejb@mulgrave.(none)|ChangeSet|20020319214738|61007 jejb@mulgrave.(none)|ChangeSet|20020311231259|61287 jejb@mulgrave.(none)|ChangeSet|20020311221007|17556 jejb@mulgrave.(none)|ChangeSet|20020311183328|17546 jejb@mulgrave.(none)|ChangeSet|20020311055930|04753 jejb@mulgrave.(none)|ChangeSet|20020311052936|04758 jejb@mulgrave.(none)|ChangeSet|20020311030012|43984 jejb@mulgrave.(none)|ChangeSet|20020311001639|42829 jejb@mulgrave.(none)|ChangeSet|20020310223507|42825 # ID: torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 # User: jejb # Host: mulgrave.(none) # Root: /home/jejb/BK/abstract-i386-2.5 # Patch vers: 1.3 # Patch type: REGULAR == ChangeSet == torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 dalecki@evision-ventures.com|ChangeSet|20020307004905|63776 D 1.375.26.1 02/03/10 17:35:07-05:00 jejb@mulgrave.(none) +24 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Split x86 into a generic component and a visws component K 42825 P ChangeSet ------------------------------------------------ 0a0 > jejb@mulgrave.(none)|arch/i386/generic/Makefile|20020310223325|12759|f0e66e5cb729acce jejb@mulgrave.(none)|arch/i386/generic/Makefile|20020310223326|44896 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020310223325|01011 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-visws.c|20020205174021|03903|8effe20055c2f553 jejb@mulgrave.(none)|arch/i386/visws/pci-visws.c|20020310152305|27108 > torvalds@athlon.transmeta.com|arch/i386/kernel/mpparse.c|20020205174021|05759|a518369612979315 jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020310223325|54934 > jejb@mulgrave.(none)|arch/i386/visws/mpparse.c|20020310223326|11757|d6f57800c1cb0c1d jejb@mulgrave.(none)|arch/i386/visws/mpparse.c|20020310223327|06758 > jejb@mulgrave.(none)|arch/i386/visws/do_timer.h|20020310223326|07933|af96030dfb8161cd jejb@mulgrave.(none)|arch/i386/visws/do_timer.h|20020310223327|55354 > jejb@mulgrave.(none)|arch/i386/generic/do_timer.h|20020310223325|26891|ec2aeb6e71be9db6 jejb@mulgrave.(none)|arch/i386/generic/do_timer.h|20020310223326|43033 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020310223325|05933 > jejb@mulgrave.(none)|arch/i386/visws/traps.c|20020310223326|15572|91a4f00b62c56fa9 jejb@mulgrave.(none)|arch/i386/visws/traps.c|20020310223327|24932 > jejb@mulgrave.(none)|arch/i386/generic/setup.c|20020310223325|30703|52beac433d138aed jejb@mulgrave.(none)|arch/i386/generic/setup.c|20020310223326|61705 > torvalds@athlon.transmeta.com|arch/i386/Makefile|20020205174020|18710|1b8aa1f0c40a1dbf jejb@mulgrave.(none)|arch/i386/Makefile|20020310223325|05334 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020310223325|53563 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-pc.c|20020205174021|63770|524c79ffe499fd6b jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020310152345|09047 > torvalds@athlon.transmeta.com|arch/i386/kernel/i8259.c|20020205174021|59798|fc99768517501f14 jejb@mulgrave.(none)|arch/i386/kernel/i8259.c|20020310223325|42500 > jejb@mulgrave.(none)|include/asm-i386/arch_hooks.h|20020310223326|19449|4214d3776d55c82 jejb@mulgrave.(none)|include/asm-i386/arch_hooks.h|20020310223327|55968 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020310223325|24982 > torvalds@athlon.transmeta.com|arch/i386/kernel/traps.c|20020205174021|43275|f01e9a814d3e2866 jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020310223325|31734 > jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c.orig|20020310223325|00088|4c5e910440eca7be jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c.orig|20020310223326|52226 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-irq.c|20020205174021|08531|4fd93b99df3a709f jejb@mulgrave.(none)|arch/i386/generic/pci-irq.c|20020310152345|13517 > patch@athlon.transmeta.com|arch/i386/kernel/setup-visws.c|20020205235942|42465|e5b21413e86afce8 jejb@mulgrave.(none)|arch/i386/visws/setup.c|20020310223325|60599 > torvalds@athlon.transmeta.com|arch/i386/kernel/visws_apic.c|20020205174021|64746|1b0f0254adaacb49 jejb@mulgrave.(none)|arch/i386/visws/visws_apic.c|20020310152250|46020 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020310223325|19362 > torvalds@athlon.transmeta.com|arch/i386/kernel/apic.c|20020205174021|04808|71c663f64b1844f0 jejb@mulgrave.(none)|arch/i386/kernel/apic.c|20020310223325|42261 > jejb@mulgrave.(none)|arch/i386/visws/Makefile|20020310223326|04124|86a8dbe92bf5299 jejb@mulgrave.(none)|arch/i386/visws/Makefile|20020310223327|48283 jejb@mulgrave.(none)|ChangeSet|20020310223507|42825 D 1.375.26.2 02/03/10 19:16:39-05:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Arch Abstraction small correction c c Add missing \n to config.in K 42829 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311001639|24992 jejb@mulgrave.(none)|ChangeSet|20020311001639|42829 D 1.375.26.3 02/03/10 22:00:12-05:00 jejb@mulgrave.(none) +4 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c X86 arch split c c Add hook for MCA NMI K 43984 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020311030012|10518 > jejb@mulgrave.(none)|arch/i386/generic/setup.c|20020310223325|30703|52beac433d138aed jejb@mulgrave.(none)|arch/i386/generic/setup.c|20020311030012|21312 > jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c.orig|20020310223325|00088|4c5e910440eca7be jejb@mulgrave.(none)|BitKeeper/deleted/.del-smpboot.c.orig~4c5e910440eca7be|20020311020511|30827 > jejb@mulgrave.(none)|include/asm-i386/arch_hooks.h|20020310223326|19449|4214d3776d55c82 jejb@mulgrave.(none)|include/asm-i386/arch_hooks.h|20020311030012|58964 jejb@mulgrave.(none)|ChangeSet|20020311030012|43984 D 1.375.26.4 02/03/11 00:29:36-05:00 jejb@mulgrave.(none) +3 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add arch split to setup.h K 4758 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311052758|36713 > jejb@mulgrave.(none)|arch/i386/visws/setup_arch.h|20020311052758|09863|129d6f33bc082b26 jejb@mulgrave.(none)|arch/i386/visws/setup_arch.h|20020311052759|57780 > jejb@mulgrave.(none)|arch/i386/generic/setup_arch.h|20020311052758|63106|f2f5d91f523e7a81 jejb@mulgrave.(none)|arch/i386/generic/setup_arch.h|20020311052759|57780 jejb@mulgrave.(none)|ChangeSet|20020311052936|04758 D 1.375.26.5 02/03/11 00:59:30-05:00 jejb@mulgrave.(none) +3 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c add ARCH_SETUP hook K 4753 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311055930|37514 > jejb@mulgrave.(none)|arch/i386/visws/setup_arch.h|20020311052758|09863|129d6f33bc082b26 jejb@mulgrave.(none)|arch/i386/visws/setup_arch.h|20020311055930|59838 > jejb@mulgrave.(none)|arch/i386/generic/setup_arch.h|20020311052758|63106|f2f5d91f523e7a81 jejb@mulgrave.(none)|arch/i386/generic/setup_arch.h|20020311055930|59838 jejb@mulgrave.(none)|ChangeSet|20020311055930|04753 D 1.375.26.6 02/03/11 13:33:28-05:00 jejb@mulgrave.(none) +5 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c More x86 arch splits c c - Make hyperthreading a separate config parameter c - split out the reboot through bios parameters K 17546 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311183147|37723 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311183147|22473 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311183147|30348 > jejb@mulgrave.(none)|arch/i386/kernel/reboot.c|20020311183147|26636|b4591d56c942a342 jejb@mulgrave.(none)|arch/i386/kernel/reboot.c|20020311183148|16068 > torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 jejb@mulgrave.(none)|arch/i386/kernel/process.c|20020311183147|63225 jejb@mulgrave.(none)|ChangeSet|20020311183328|17546 D 1.375.26.7 02/03/11 17:10:07-05:00 jejb@mulgrave.(none) +6 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c More Separation c c - add do_timer_overflow() function for coping with tick overflow c - make find_smp_config() gated by its own define c - bug fixes and corrections K 17556 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311220844|38137 > torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020311220844|13032 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020311220844|34025 > jejb@mulgrave.(none)|arch/i386/visws/do_timer.h|20020310223326|07933|af96030dfb8161cd jejb@mulgrave.(none)|arch/i386/visws/do_timer.h|20020311220844|33373 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311220844|54491 > jejb@mulgrave.(none)|arch/i386/generic/do_timer.h|20020310223325|26891|ec2aeb6e71be9db6 jejb@mulgrave.(none)|arch/i386/generic/do_timer.h|20020311220844|51068 torvalds@penguin.transmeta.com|ChangeSet|20020308015057|44839 D 1.384.9.1 02/03/11 18:12:59-05:00 jejb@mulgrave.(none) +6 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge mulgrave.(none):/home/jejb/BK/linux-2.5 c into mulgrave.(none):/home/jejb/BK/abstract-i386-2.5 i jejb@mulgrave.(none)|ChangeSet|20020310223507|42825 i jejb@mulgrave.(none)|ChangeSet|20020311001639|42829 i jejb@mulgrave.(none)|ChangeSet|20020311030012|43984 i jejb@mulgrave.(none)|ChangeSet|20020311052936|04758 i jejb@mulgrave.(none)|ChangeSet|20020311055930|04753 i jejb@mulgrave.(none)|ChangeSet|20020311183328|17546 i jejb@mulgrave.(none)|ChangeSet|20020311221007|17556 K 61287 M jejb@mulgrave.(none)|ChangeSet|20020311221007|17556 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/mpparse.c|20020205174021|05759|a518369612979315 jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020311231258|08258 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-pc.c|20020205174021|63770|524c79ffe499fd6b jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020311231258|01926 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311231257|23093 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020311231257|10129 > torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311231258|56833 > torvalds@athlon.transmeta.com|arch/i386/kernel/traps.c|20020205174021|43275|f01e9a814d3e2866 jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020311231258|34761 torvalds@home.transmeta.com|ChangeSet|20020318194024|46827 D 1.538 02/03/19 13:47:38-08:00 jejb@mulgrave.(none) +8 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge By hand i jejb@mulgrave.(none)|ChangeSet|20020311231259|61287 K 61007 M jejb@mulgrave.(none)|ChangeSet|20020311231259|61287 P ChangeSet ------------------------------------------------ 0a0 > torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020319214140|10202 > torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020319214737|21971 > torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 jejb@mulgrave.(none)|arch/i386/config.in|20020319214139|34900 > torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020319214140|58542 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-pc.c|20020205174021|63770|524c79ffe499fd6b jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020319214140|50253 > torvalds@athlon.transmeta.com|arch/i386/kernel/traps.c|20020205174021|43275|f01e9a814d3e2866 jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020319214140|01407 > torvalds@athlon.transmeta.com|arch/i386/kernel/pci-irq.c|20020205174021|08531|4fd93b99df3a709f jejb@mulgrave.(none)|arch/i386/generic/pci-irq.c|20020319214139|64973 > torvalds@athlon.transmeta.com|arch/i386/kernel/mpparse.c|20020205174021|05759|a518369612979315 jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020319214139|52912 == arch/i386/generic/Makefile == New file: arch/i386/generic/Makefile V 4 jejb@mulgrave.(none)|arch/i386/generic/Makefile|20020310223325|12759|f0e66e5cb729acce D 1.0 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/generic/Makefile K 12759 P arch/i386/generic/Makefile R f0e66e5cb729acce X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/Makefile|20020310223325|12759|f0e66e5cb729acce D 1.1 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +24 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 44896 O -rw-rw-r-- P arch/i386/generic/Makefile ------------------------------------------------ I0 24 # # Makefile for the linux kernel. # # Note! Dependencies are done automagically by 'make dep', which also # removes any old dependencies. DON'T put your own dependencies here # unless it's something special (ie not a .c file). # # Note 2! The CFLAGS definitions are now in the main makefile... \ .S.o: $(CC) $(AFLAGS) -traditional -c $< -o $*.o \ all: generic.o \ O_TARGET := generic.o EXTRA_CFLAGS += -I../kernel export-objs := \ obj-y := setup.o \ obj-$(CONFIG_PCI) += pci-pc.o pci-irq.o obj-$(CONFIG_X86_LOCAL_APIC) += mpparse.o \ include $(TOPDIR)/Rules.make == arch/i386/generic/do_timer.h == New file: arch/i386/generic/do_timer.h V 4 jejb@mulgrave.(none)|arch/i386/generic/do_timer.h|20020310223325|26891|ec2aeb6e71be9db6 D 1.0 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/generic/do_timer.h K 26891 P arch/i386/generic/do_timer.h R ec2aeb6e71be9db6 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/do_timer.h|20020310223325|26891|ec2aeb6e71be9db6 D 1.1 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +18 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 43033 O -rw-rw-r-- P arch/i386/generic/do_timer.h ------------------------------------------------ I0 18 /* defines for inline arch setup functions */ \ static inline void do_timer_interrupt_hook(struct pt_regs *regs) { do_timer(regs); /* * In the SMP case we use the local APIC timer interrupt to do the * profiling, except when we simulate SMP mode on a uniprocessor * system, in that case we have to call the local interrupt handler. */ #ifndef CONFIG_X86_LOCAL_APIC if (!user_mode(regs)) x86_do_profile(regs->eip); #else if (!using_apic_timer) smp_local_timer_interrupt(regs); #endif } jejb@mulgrave.(none)|arch/i386/generic/do_timer.h|20020310223326|43033 D 1.2 02/03/11 17:08:44-05:00 jejb@mulgrave.(none) +43 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add do_timer_overflow abstraction K 51068 O -rw-rw-r-- P arch/i386/generic/do_timer.h ------------------------------------------------ I18 43 \ \ /* you can safely undefine this if you don't have the Neptune chipset */ \ #define BUGGY_NEPTUN_TIMER \ static inline int do_timer_overflow(int count) { int i; \ spin_lock(&i8259A_lock); /* * This is tricky when I/O APICs are used; * see do_timer_interrupt(). */ i = inb(0x20); spin_unlock(&i8259A_lock); /* assumption about timer being IRQ0 */ if (i & 0x01) { /* * We cannot detect lost timer interrupts ... * well, that's why we call them lost, don't we? :) * [hmm, on the Pentium and Alpha we can ... sort of] */ count -= LATCH; } else { #ifdef BUGGY_NEPTUN_TIMER /* * for the Neptun bug we know that the 'latch' * command doesnt latch the high and low value * of the counter atomically. Thus we have to * substract 256 from the counter * ... funny, isnt it? :) */ count -= 256; #else printk("do_slow_gettimeoffset(): hardware timer problem?\n"); #endif } return count; } == arch/i386/generic/setup.c == New file: arch/i386/generic/setup.c V 4 jejb@mulgrave.(none)|arch/i386/generic/setup.c|20020310223325|30703|52beac433d138aed D 1.0 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/generic/setup.c K 30703 P arch/i386/generic/setup.c R 52beac433d138aed X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/setup.c|20020310223325|30703|52beac433d138aed D 1.1 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +43 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 61705 O -rw-rw-r-- P arch/i386/generic/setup.c ------------------------------------------------ I0 43 /* * Machine specific setup for generic */ \ #include #include #include #include #include \ void __init pre_intr_init_hook(void) { init_ISA_irqs(); } \ /* * IRQ2 is cascade interrupt to second interrupt controller */ static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL}; \ void __init intr_init_hook(void) { #ifdef CONFIG_X86_LOCAL_APIC apic_intr_init(); #endif \ setup_irq(2, &irq2); } \ void __init pre_setup_arch_hook(void) { } \ void __init trap_init_hook(void) { } \ static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL}; \ void __init time_init_hook(void) { setup_irq(0, &irq0); } jejb@mulgrave.(none)|arch/i386/generic/setup.c|20020310223326|61705 D 1.2 02/03/10 22:00:12-05:00 jejb@mulgrave.(none) +13 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c add mca nmi hook K 21312 O -rw-rw-r-- P arch/i386/generic/setup.c ------------------------------------------------ I4 1 #include I43 12 \ #ifdef CONFIG_MCA void __init mca_nmi_hook(void) { /* If I recall correctly, there's a whole bunch of other things that * we can do to check for NMI problems, but that's all I know about * at the moment. */ \ printk("NMI generated from unknown source!\n"); } #endif == arch/i386/generic/setup_arch.h == New file: arch/i386/generic/setup_arch.h V 4 jejb@mulgrave.(none)|arch/i386/generic/setup_arch.h|20020311052758|63106|f2f5d91f523e7a81 D 1.0 02/03/11 00:27:58-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/generic/setup_arch.h K 63106 P arch/i386/generic/setup_arch.h R f2f5d91f523e7a81 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/setup_arch.h|20020311052758|63106|f2f5d91f523e7a81 D 1.1 02/03/11 00:27:58-05:00 jejb@mulgrave.(none) +34 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 57780 O -rw-rw-r-- P arch/i386/generic/setup_arch.h ------------------------------------------------ I0 34 #ifdef SETUP_POST static inline char * __init machine_specific_memory_setup(void) { char *who; \ \ who = "BIOS-e820"; \ /* * Try to copy the BIOS-supplied E820-map. * * Otherwise fake a memory map; one section from 0k->640k, * the next section from 1mb->appropriate_mem_k */ sanitize_e820_map(E820_MAP, &E820_MAP_NR); if (copy_e820_map(E820_MAP, E820_MAP_NR) < 0) { unsigned long mem_size; \ /* compare results from other methods and take the greater */ if (ALT_MEM_K < EXT_MEM_K) { mem_size = EXT_MEM_K; who = "BIOS-88"; } else { mem_size = ALT_MEM_K; who = "BIOS-e801"; } \ e820.nr_map = 0; add_memory_region(0, LOWMEMSIZE(), E820_RAM); add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM); } return who; } #endif jejb@mulgrave.(none)|arch/i386/generic/setup_arch.h|20020311052759|57780 D 1.2 02/03/11 00:59:30-05:00 jejb@mulgrave.(none) +3 -1 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c add ARCH_SETUP hook K 59838 O -rw-rw-r-- P arch/i386/generic/setup_arch.h ------------------------------------------------ D1 1 I1 3 #ifndef SETUP_POST #define ARCH_SETUP #else == arch/i386/kernel/reboot.c == New file: arch/i386/kernel/reboot.c V 4 jejb@mulgrave.(none)|arch/i386/kernel/reboot.c|20020311183147|26636|b4591d56c942a342 D 1.0 02/03/11 13:31:47-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/kernel/reboot.c K 26636 P arch/i386/kernel/reboot.c R b4591d56c942a342 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/kernel/reboot.c|20020311183147|26636|b4591d56c942a342 D 1.1 02/03/11 13:31:47-05:00 jejb@mulgrave.(none) +329 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 16068 O -rw-rw-r-- P arch/i386/kernel/reboot.c ------------------------------------------------ I0 329 /* * linux/arch/i386/kernel/reboot.c */ \ #define __KERNEL_SYSCALLS__ #include \ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include \ #include #include #include #include #include #include #include #include #ifdef CONFIG_MATH_EMULATION #include #endif \ #include #include \ /* * Power off function, if any */ void (*pm_power_off)(void); \ static long no_idt[2]; static int reboot_mode; int reboot_thru_bios; \ #ifdef CONFIG_SMP int reboot_smp = 0; static int reboot_cpu = -1; /* shamelessly grabbed from lib/vsprintf.c for readability */ #define is_digit(c) ((c) >= '0' && (c) <= '9') #endif static int __init reboot_setup(char *str) { while(1) { switch (*str) { case 'w': /* "warm" reboot (no memory testing etc) */ reboot_mode = 0x1234; break; case 'c': /* "cold" reboot (with memory testing etc) */ reboot_mode = 0x0; break; case 'b': /* "bios" reboot by jumping through the BIOS */ reboot_thru_bios = 1; break; case 'h': /* "hard" reboot by toggling RESET and/or crashing the CPU */ reboot_thru_bios = 0; break; #ifdef CONFIG_SMP case 's': /* "smp" reboot by executing reset on BSP or other CPU*/ reboot_smp = 1; if (is_digit(*(str+1))) { reboot_cpu = (int) (*(str+1) - '0'); if (is_digit(*(str+2))) reboot_cpu = reboot_cpu*10 + (int)(*(str+2) - '0'); } /* we will leave sorting out the final value when we are ready to reboot, since we might not have set up boot_cpu_id or smp_num_cpu */ break; #endif } if((str = strchr(str,',')) != NULL) str++; else break; } return 1; } \ __setup("reboot=", reboot_setup); \ /* The following code and data reboots the machine by switching to real mode and jumping to the BIOS reset entry point, as if the CPU has really been reset. The previous version asked the keyboard controller to pulse the CPU reset line, which is more thorough, but doesn't work with at least one type of 486 motherboard. It is easy to stop this code working; hence the copious comments. */ \ static unsigned long long real_mode_gdt_entries [3] = { 0x0000000000000000ULL, /* Null descriptor */ 0x00009a000000ffffULL, /* 16-bit real-mode 64k code at 0x00000000 */ 0x000092000100ffffULL /* 16-bit real-mode 64k data at 0x00000100 */ }; \ static struct { unsigned short size __attribute__ ((packed)); unsigned long long * base __attribute__ ((packed)); } real_mode_gdt = { sizeof (real_mode_gdt_entries) - 1, real_mode_gdt_entries }, real_mode_idt = { 0x3ff, 0 }; \ /* This is 16-bit protected mode code to disable paging and the cache, switch to real mode and jump to the BIOS reset code. \ The instruction that switches to real mode by writing to CR0 must be followed immediately by a far jump instruction, which set CS to a valid value for real mode, and flushes the prefetch queue to avoid running instructions that have already been decoded in protected mode. \ Clears all the flags except ET, especially PG (paging), PE (protected-mode enable) and TS (task switch for coprocessor state save). Flushes the TLB after paging has been disabled. Sets CD and NW, to disable the cache on a 486, and invalidates the cache. This is more like the state of a 486 after reset. I don't know if something else should be done for other chips. \ More could be done here to set up the registers as if a CPU reset had occurred; hopefully real BIOSs don't assume much. */ \ static unsigned char real_mode_switch [] = { 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ 0x66, 0x83, 0xe0, 0x11, /* andl $0x00000011,%eax */ 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */ 0x66, 0x0f, 0x22, 0xc0, /* movl %eax,%cr0 */ 0x66, 0x0f, 0x22, 0xd8, /* movl %eax,%cr3 */ 0x66, 0x0f, 0x20, 0xc3, /* movl %cr0,%ebx */ 0x66, 0x81, 0xe3, 0x00, 0x00, 0x00, 0x60, /* andl $0x60000000,%ebx */ 0x74, 0x02, /* jz f */ 0x0f, 0x08, /* invd */ 0x24, 0x10, /* f: andb $0x10,al */ 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ }; static unsigned char jump_to_bios [] = { 0xea, 0x00, 0x00, 0xff, 0xff /* ljmp $0xffff,$0x0000 */ }; \ static inline void kb_wait(void) { int i; \ for (i=0; i<0x10000; i++) if ((inb_p(0x64) & 0x02) == 0) break; } \ /* * Switch to real mode and then execute the code * specified by the code and length parameters. * We assume that length will aways be less that 100! */ void machine_real_restart(unsigned char *code, int length) { unsigned long flags; \ cli(); \ /* Write zero to CMOS register number 0x0f, which the BIOS POST routine will recognize as telling it to do a proper reboot. (Well that's what this book in front of me says -- it may only apply to the Phoenix BIOS though, it's not clear). At the same time, disable NMIs by setting the top bit in the CMOS address register, as we're about to do peculiar things to the CPU. I'm not sure if `outb_p' is needed instead of just `outb'. Use it to be on the safe side. (Yes, CMOS_WRITE does outb_p's. - Paul G.) */ \ spin_lock_irqsave(&rtc_lock, flags); CMOS_WRITE(0x00, 0x8f); spin_unlock_irqrestore(&rtc_lock, flags); \ /* Remap the kernel at virtual address zero, as well as offset zero from the kernel segment. This assumes the kernel segment starts at virtual address PAGE_OFFSET. */ \ memcpy (swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, sizeof (swapper_pg_dir [0]) * KERNEL_PGD_PTRS); \ /* Make sure the first page is mapped to the start of physical memory. It is normally not mapped, to trap kernel NULL pointer dereferences. */ \ pg0[0] = _PAGE_RW | _PAGE_PRESENT; \ /* * Use `swapper_pg_dir' as our page directory. */ asm volatile("movl %0,%%cr3": :"r" (__pa(swapper_pg_dir))); \ /* Write 0x1234 to absolute memory location 0x472. The BIOS reads this on booting to tell it to "Bypass memory test (also warm boot)". This seems like a fairly standard thing that gets set by REBOOT.COM programs, and the previous reset routine did this too. */ \ *((unsigned short *)0x472) = reboot_mode; \ /* For the switch to real mode, copy some code to low memory. It has to be in the first 64k because it is running in 16-bit mode, and it has to have the same physical and virtual address, because it turns off paging. Copy it near the end of the first page, out of the way of BIOS variables. */ \ memcpy ((void *) (0x1000 - sizeof (real_mode_switch) - 100), real_mode_switch, sizeof (real_mode_switch)); memcpy ((void *) (0x1000 - 100), code, length); \ /* Set up the IDT for real mode. */ \ __asm__ __volatile__ ("lidt %0" : : "m" (real_mode_idt)); \ /* Set up a GDT from which we can load segment descriptors for real mode. The GDT is not used in real mode; it is just needed here to prepare the descriptors. */ \ __asm__ __volatile__ ("lgdt %0" : : "m" (real_mode_gdt)); \ /* Load the data segment registers, and thus the descriptors ready for real mode. The base address of each segment is 0x100, 16 times the selector value being loaded here. This is so that the segment registers don't have to be reloaded after switching to real mode: the values are consistent for real mode operation already. */ \ __asm__ __volatile__ ("movl $0x0010,%%eax\n" "\tmovl %%eax,%%ds\n" "\tmovl %%eax,%%es\n" "\tmovl %%eax,%%fs\n" "\tmovl %%eax,%%gs\n" "\tmovl %%eax,%%ss" : : : "eax"); \ /* Jump to the 16-bit code that we copied earlier. It disables paging and the cache, switches to real mode, and jumps to the BIOS reset entry point. */ \ __asm__ __volatile__ ("ljmp $0x0008,%0" : : "i" ((void *) (0x1000 - sizeof (real_mode_switch) - 100))); } \ void machine_restart(char * __unused) { #if CONFIG_SMP int cpuid; cpuid = GET_APIC_ID(apic_read(APIC_ID)); \ if (reboot_smp) { \ /* check to see if reboot_cpu is valid if its not, default to the BSP */ if ((reboot_cpu == -1) || (reboot_cpu > (NR_CPUS -1)) || !(phys_cpu_present_map & (1< * (c) 1998, 1999, 2000 Ingo Molnar * * Much of the core SMP work is based on previous work by Thomas Radke, to * whom a great many thanks are extended. * * Thanks to Intel for making available several different Pentium, * Pentium Pro and Pentium-II/Xeon MP machines. * Original development of Linux SMP code supported by Caldera. * * This code is released under the GNU General Public License version 2 or * later. * * Fixes * Felix Koop : NR_CPUS used properly * Jose Renau : Handle single CPU case. * Alan Cox : By repeated request 8) - Total BogoMIP report. * Greg Wright : Fix for kernel stacks panic. * Erich Boleyn : MP v1.4 and additional changes. * Matthias Sattler : Changes for 2.1 kernel map. * Michel Lespinasse : Changes for 2.1 kernel map. * Michael Chastain : Change trampoline.S to gnu as. * Alan Cox : Dumb bug: 'B' step PPro's are fine * Ingo Molnar : Added APIC timers, based on code * from Jose Renau * Ingo Molnar : various cleanups and rewrites * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. * Maciej W. Rozycki : Bits for genuine 82489DX APICs * Martin J. Bligh : Added support for multi-quad systems * Dave Jones : Report invalid combinations of Athlon CPUs. */ \ #include #include #include \ #include #include #include #include #include \ #include #include #include #include #include \ /* Set if we find a B stepping CPU */ static int smp_b_stepping; \ /* Setup configured maximum number of CPUs to activate */ static int max_cpus = -1; \ /* Total count of live CPUs */ int smp_num_cpus = 1; \ /* Number of siblings per CPU package */ int smp_num_siblings = 1; int __initdata phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */ \ /* Bitmask of currently online CPUs */ unsigned long cpu_online_map; \ static volatile unsigned long cpu_callin_map; static volatile unsigned long cpu_callout_map; \ /* Per CPU bogomips and other parameters */ struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; \ /* Set when the idlers are all forked */ int smp_threads_ready; \ /* * Setup routine for controlling SMP activation * * Command-line option of "nosmp" or "maxcpus=0" will disable SMP * activation entirely (the MPS table probe still happens, though). * * Command-line option of "maxcpus=", where is an integer * greater than 0, limits the maximum number of CPUs activated in * SMP mode to . */ \ static int __init nosmp(char *str) { max_cpus = 0; return 1; } \ __setup("nosmp", nosmp); \ static int __init maxcpus(char *str) { get_option(&str, &max_cpus); return 1; } \ __setup("maxcpus=", maxcpus); \ /* * Trampoline 80x86 program as an array. */ \ extern unsigned char trampoline_data []; extern unsigned char trampoline_end []; static unsigned char *trampoline_base; \ /* * Currently trivial. Write the real->protected mode * bootstrap into the page concerned. The caller * has made sure it's suitably aligned. */ \ static unsigned long __init setup_trampoline(void) { memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); return virt_to_phys(trampoline_base); } \ /* * We are called very early to get the low memory for the * SMP bootup trampoline page. */ void __init smp_alloc_memory(void) { trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); /* * Has to be in very low memory so we can execute * real-mode AP code. */ if (__pa(trampoline_base) >= 0x9F000) BUG(); } \ /* * The bootstrap kernel entry code has set these up. Save them for * a given CPU */ \ void __init smp_store_cpu_info(int id) { struct cpuinfo_x86 *c = cpu_data + id; \ *c = boot_cpu_data; identify_cpu(c); /* * Mask B, Pentium, but not Pentium MMX */ if (c->x86_vendor == X86_VENDOR_INTEL && c->x86 == 5 && c->x86_mask >= 1 && c->x86_mask <= 4 && c->x86_model <= 3) /* * Remember we have B step Pentia with bugs */ smp_b_stepping = 1; \ /* * Certain Athlons might work (for various values of 'work') in SMP * but they are not certified as MP capable. */ if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { \ /* Athlon 660/661 is valid. */ if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) goto valid_k7; \ /* Duron 670 is valid */ if ((c->x86_model==7) && (c->x86_mask==0)) goto valid_k7; \ /* Athlon 662, Duron 671, and Athlon >model 7 have capability bit */ if (((c->x86_model==6) && (c->x86_mask>=2)) || ((c->x86_model==7) && (c->x86_mask>=1)) || (c->x86_model> 7)) if (cpu_has_mp) goto valid_k7; \ /* If we get here, it's not a certified SMP capable AMD system. */ printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); tainted |= TAINT_UNSAFE_SMP; } valid_k7: \ } \ /* * Architecture specific routine called by the kernel just before init is * fired off. This allows the BP to have everything in order [we hope]. * At the end of this all the APs will hit the system scheduling and off * we go. Each AP will load the system gdt's and jump through the kernel * init into idle(). At this point the scheduler will one day take over * and give them jobs to do. smp_callin is a standard routine * we use to track CPUs as they power up. */ \ static atomic_t smp_commenced = ATOMIC_INIT(0); \ void __init smp_commence(void) { /* * Lets the callins below out of their loop. */ Dprintk("Setting commenced=1, go go go\n"); \ wmb(); atomic_set(&smp_commenced,1); } \ /* * TSC synchronization. * * We first check wether all CPUs have their TSC's synchronized, * then we print a warning if not, and always resync. */ \ static atomic_t tsc_start_flag = ATOMIC_INIT(0); static atomic_t tsc_count_start = ATOMIC_INIT(0); static atomic_t tsc_count_stop = ATOMIC_INIT(0); static unsigned long long tsc_values[NR_CPUS]; \ #define NR_LOOPS 5 \ extern unsigned long fast_gettimeoffset_quotient; \ /* * accurate 64-bit/32-bit division, expanded to 32-bit divisions and 64-bit * multiplication. Not terribly optimized but we need it at boot time only * anyway. * * result == a / b * == (a1 + a2*(2^32)) / b * == a1/b + a2*(2^32/b) * == a1/b + a2*((2^32-1)/b) + a2/b + (a2*((2^32-1) % b))/b * ^---- (this multiplication can overflow) */ \ static unsigned long long __init div64 (unsigned long long a, unsigned long b0) { unsigned int a1, a2; unsigned long long res; \ a1 = ((unsigned int*)&a)[0]; a2 = ((unsigned int*)&a)[1]; \ res = a1/b0 + (unsigned long long)a2 * (unsigned long long)(0xffffffff/b0) + a2 / b0 + (a2 * (0xffffffff % b0)) / b0; \ return res; } \ static void __init synchronize_tsc_bp (void) { int i; unsigned long long t0; unsigned long long sum, avg; long long delta; unsigned long one_usec; int buggy = 0; \ printk("checking TSC synchronization across CPUs: "); \ one_usec = ((1<<30)/fast_gettimeoffset_quotient)*(1<<2); \ atomic_set(&tsc_start_flag, 1); wmb(); \ /* * We loop a few times to get a primed instruction cache, * then the last pass is more or less synchronized and * the BP and APs set their cycle counters to zero all at * once. This reduces the chance of having random offsets * between the processors, and guarantees that the maximum * delay between the cycle counters is never bigger than * the latency of information-passing (cachelines) between * two CPUs. */ for (i = 0; i < NR_LOOPS; i++) { /* * all APs synchronize but they loop on '== num_cpus' */ while (atomic_read(&tsc_count_start) != smp_num_cpus-1) mb(); atomic_set(&tsc_count_stop, 0); wmb(); /* * this lets the APs save their current TSC: */ atomic_inc(&tsc_count_start); \ rdtscll(tsc_values[smp_processor_id()]); /* * We clear the TSC in the last loop: */ if (i == NR_LOOPS-1) write_tsc(0, 0); \ /* * Wait for all APs to leave the synchronization point: */ while (atomic_read(&tsc_count_stop) != smp_num_cpus-1) mb(); atomic_set(&tsc_count_start, 0); wmb(); atomic_inc(&tsc_count_stop); } \ sum = 0; for (i = 0; i < smp_num_cpus; i++) { t0 = tsc_values[i]; sum += t0; } avg = div64(sum, smp_num_cpus); \ sum = 0; for (i = 0; i < smp_num_cpus; i++) { delta = tsc_values[i] - avg; if (delta < 0) delta = -delta; /* * We report bigger than 2 microseconds clock differences. */ if (delta > 2*one_usec) { long realdelta; if (!buggy) { buggy = 1; printk("\n"); } realdelta = div64(delta, one_usec); if (tsc_values[i] < avg) realdelta = -realdelta; \ printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n", i, realdelta); } \ sum += delta; } if (!buggy) printk("passed.\n"); ; } \ static void __init synchronize_tsc_ap (void) { int i; \ /* * smp_num_cpus is not necessarily known at the time * this gets called, so we first wait for the BP to * finish SMP initialization: */ while (!atomic_read(&tsc_start_flag)) mb(); \ for (i = 0; i < NR_LOOPS; i++) { atomic_inc(&tsc_count_start); while (atomic_read(&tsc_count_start) != smp_num_cpus) mb(); \ rdtscll(tsc_values[smp_processor_id()]); if (i == NR_LOOPS-1) write_tsc(0, 0); \ atomic_inc(&tsc_count_stop); while (atomic_read(&tsc_count_stop) != smp_num_cpus) mb(); } } #undef NR_LOOPS \ extern void calibrate_delay(void); \ static atomic_t init_deasserted; \ void __init smp_callin(void) { int cpuid, phys_id; unsigned long timeout; \ /* * If waken up by an INIT in an 82489DX configuration * we may get here before an INIT-deassert IPI reaches * our local APIC. We have to wait for the IPI or we'll * lock up on an APIC access. */ if (!clustered_apic_mode) while (!atomic_read(&init_deasserted)); \ /* * (This works even if the APIC is not enabled.) */ phys_id = GET_APIC_ID(apic_read(APIC_ID)); cpuid = smp_processor_id(); if (test_and_set_bit(cpuid, &cpu_online_map)) { printk("huh, phys CPU#%d, CPU#%d already present??\n", phys_id, cpuid); BUG(); } Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); \ /* * STARTUP IPIs are fragile beasts as they might sometimes * trigger some glue motherboard logic. Complete APIC bus * silence for 1 second, this overestimates the time the * boot CPU is spending to send the up to 2 STARTUP IPIs * by a factor of two. This should be enough. */ \ /* * Waiting 2s total for startup (udelay is not yet working) */ timeout = jiffies + 2*HZ; while (time_before(jiffies, timeout)) { /* * Has the boot CPU finished it's STARTUP sequence? */ if (test_bit(cpuid, &cpu_callout_map)) break; rep_nop(); } \ if (!time_before(jiffies, timeout)) { printk("BUG: CPU%d started up but did not get a callout!\n", cpuid); BUG(); } \ /* * the boot CPU has finished the init stage and is spinning * on callin_map until we finish. We are free to set up this * CPU, first the APIC. (this is probably redundant on most * boards) */ \ Dprintk("CALLIN, before setup_local_APIC().\n"); /* * Because we use NMIs rather than the INIT-STARTUP sequence to * bootstrap the CPUs, the APIC may be in a wierd state. Kick it. */ if (clustered_apic_mode) clear_local_APIC(); setup_local_APIC(); \ __sti(); \ #ifdef CONFIG_MTRR /* * Must be done before calibration delay is computed */ mtrr_init_secondary_cpu (); #endif /* * Get our bogomips. */ calibrate_delay(); Dprintk("Stack at about %p\n",&cpuid); \ /* * Save our processor parameters */ smp_store_cpu_info(cpuid); \ disable_APIC_timer(); /* * Allow the master to continue. */ set_bit(cpuid, &cpu_callin_map); \ /* * Synchronize the TSC with the BP */ if (cpu_has_tsc) synchronize_tsc_ap(); } \ int cpucount; \ extern int cpu_idle(void); \ /* * Activate a secondary processor. */ int __init start_secondary(void *unused) { /* * Dont put anything before smp_callin(), SMP * booting is too fragile that we want to limit the * things done here to the most necessary things. */ cpu_init(); smp_callin(); while (!atomic_read(&smp_commenced)) rep_nop(); enable_APIC_timer(); /* * low-memory mappings have been cleared, flush them from * the local TLBs too. */ local_flush_tlb(); \ return cpu_idle(); } \ /* * Everything has been set up for the secondary * CPUs - they just need to reload everything * from the task structure * This function must not return. */ void __init initialize_secondary(void) { /* * We don't actually need to load the full TSS, * basically just the stack pointer and the eip. */ \ asm volatile( "movl %0,%%esp\n\t" "jmp *%1" : :"r" (current->thread.esp),"r" (current->thread.eip)); } \ extern struct { void * esp; unsigned short ss; } stack_start; \ static int __init fork_by_hand(void) { struct pt_regs regs; /* * don't care about the eip and regs settings since * we'll never reschedule the forked task. */ return do_fork(CLONE_VM|CLONE_PID, 0, ®s, 0); } \ /* which physical APIC ID maps to which logical CPU number */ volatile int physical_apicid_2_cpu[MAX_APICID]; /* which logical CPU number maps to which physical APIC ID */ volatile int cpu_2_physical_apicid[NR_CPUS]; \ /* which logical APIC ID maps to which logical CPU number */ volatile int logical_apicid_2_cpu[MAX_APICID]; /* which logical CPU number maps to which logical APIC ID */ volatile int cpu_2_logical_apicid[NR_CPUS]; \ static inline void init_cpu_to_apicid(void) /* Initialize all maps between cpu number and apicids */ { int apicid, cpu; \ for (apicid = 0; apicid < MAX_APICID; apicid++) { physical_apicid_2_cpu[apicid] = -1; logical_apicid_2_cpu[apicid] = -1; } for (cpu = 0; cpu < NR_CPUS; cpu++) { cpu_2_physical_apicid[cpu] = -1; cpu_2_logical_apicid[cpu] = -1; } } \ static inline void map_cpu_to_boot_apicid(int cpu, int apicid) /* * set up a mapping between cpu and apicid. Uses logical apicids for multiquad, * else physical apic ids */ { if (clustered_apic_mode) { logical_apicid_2_cpu[apicid] = cpu; cpu_2_logical_apicid[cpu] = apicid; } else { physical_apicid_2_cpu[apicid] = cpu; cpu_2_physical_apicid[cpu] = apicid; } } \ static inline void unmap_cpu_to_boot_apicid(int cpu, int apicid) /* * undo a mapping between cpu and apicid. Uses logical apicids for multiquad, * else physical apic ids */ { if (clustered_apic_mode) { logical_apicid_2_cpu[apicid] = -1; cpu_2_logical_apicid[cpu] = -1; } else { physical_apicid_2_cpu[apicid] = -1; cpu_2_physical_apicid[cpu] = -1; } } \ #if APIC_DEBUG static inline void inquire_remote_apic(int apicid) { int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; char *names[] = { "ID", "VERSION", "SPIV" }; int timeout, status; \ printk("Inquiring remote APIC #%d...\n", apicid); \ for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { printk("... APIC #%d %s: ", apicid, names[i]); \ /* * Wait for idle. */ apic_wait_icr_idle(); \ apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); \ timeout = 0; do { udelay(100); status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); \ switch (status) { case APIC_ICR_RR_VALID: status = apic_read(APIC_RRR); printk("%08x\n", status); break; default: printk("failed\n"); } } } #endif \ static int wakeup_secondary_via_NMI(int logical_apicid) /* * Poke the other CPU in the eye to wake it up. Remember that the normal * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this * won't ... remember to clear down the APIC, etc later. */ { unsigned long send_status = 0, accept_status = 0; int timeout, maxlvt; \ /* Target chip */ apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); \ /* Boot on the stack */ /* Kick the second */ apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); \ Dprintk("Waiting for send to finish...\n"); timeout = 0; do { Dprintk("+"); udelay(100); send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); \ /* * Give the other CPU some time to accept the IPI. */ udelay(200); /* * Due to the Pentium erratum 3AP. */ maxlvt = get_maxlvt(); if (maxlvt > 3) { apic_read_around(APIC_SPIV); apic_write(APIC_ESR, 0); } accept_status = (apic_read(APIC_ESR) & 0xEF); Dprintk("NMI sent.\n"); \ if (send_status) printk("APIC never delivered???\n"); if (accept_status) printk("APIC delivery error (%lx).\n", accept_status); \ return (send_status | accept_status); } \ static int wakeup_secondary_via_INIT(int phys_apicid, unsigned long start_eip) { unsigned long send_status = 0, accept_status = 0; int maxlvt, timeout, num_starts, j; \ Dprintk("Asserting INIT.\n"); \ /* * Turn INIT on target chip */ apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); \ /* * Send IPI */ apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); \ Dprintk("Waiting for send to finish...\n"); timeout = 0; do { Dprintk("+"); udelay(100); send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); \ mdelay(10); \ Dprintk("Deasserting INIT.\n"); \ /* Target chip */ apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); \ /* Send IPI */ apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); \ Dprintk("Waiting for send to finish...\n"); timeout = 0; do { Dprintk("+"); udelay(100); send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); \ atomic_set(&init_deasserted, 1); \ /* * Should we send STARTUP IPIs ? * * Determine this based on the APIC version. * If we don't have an integrated APIC, don't send the STARTUP IPIs. */ if (APIC_INTEGRATED(apic_version[phys_apicid])) num_starts = 2; else num_starts = 0; \ /* * Run STARTUP IPI loop. */ Dprintk("#startup loops: %d.\n", num_starts); \ maxlvt = get_maxlvt(); \ for (j = 1; j <= num_starts; j++) { Dprintk("Sending STARTUP #%d.\n",j); apic_read_around(APIC_SPIV); apic_write(APIC_ESR, 0); apic_read(APIC_ESR); Dprintk("After apic_write.\n"); \ /* * STARTUP IPI */ \ /* Target chip */ apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); \ /* Boot on the stack */ /* Kick the second */ apic_write_around(APIC_ICR, APIC_DM_STARTUP | (start_eip >> 12)); \ /* * Give the other CPU some time to accept the IPI. */ udelay(300); \ Dprintk("Startup point 1.\n"); \ Dprintk("Waiting for send to finish...\n"); timeout = 0; do { Dprintk("+"); udelay(100); send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); \ /* * Give the other CPU some time to accept the IPI. */ udelay(200); /* * Due to the Pentium erratum 3AP. */ if (maxlvt > 3) { apic_read_around(APIC_SPIV); apic_write(APIC_ESR, 0); } accept_status = (apic_read(APIC_ESR) & 0xEF); if (send_status || accept_status) break; } Dprintk("After Startup.\n"); \ if (send_status) printk("APIC never delivered???\n"); if (accept_status) printk("APIC delivery error (%lx).\n", accept_status); \ return (send_status | accept_status); } \ extern unsigned long cpu_initialized; \ static void __init do_boot_cpu (int apicid) /* * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad * (ie clustered apic addressing mode), this is a LOGICAL apic ID. */ { struct task_struct *idle; unsigned long boot_error = 0; int timeout, cpu; unsigned long start_eip; unsigned short nmi_high, nmi_low; \ cpu = ++cpucount; /* * We can't use kernel_thread since we must avoid to * reschedule the child. */ if (fork_by_hand() < 0) panic("failed fork for CPU %d", cpu); \ /* * We remove it from the pidhash and the runqueue * once we got the process: */ idle = init_task.prev_task; if (!idle) panic("No idle process for CPU %d", cpu); \ init_idle(idle, cpu); \ map_cpu_to_boot_apicid(cpu, apicid); \ idle->thread.eip = (unsigned long) start_secondary; \ unhash_process(idle); \ /* start_eip had better be page-aligned! */ start_eip = setup_trampoline(); \ /* So we see what's up */ printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); stack_start.esp = (void *) (1024 + PAGE_SIZE + (char *)idle->thread_info); \ /* * This grunge runs the startup process for * the targeted processor. */ \ atomic_set(&init_deasserted, 0); \ Dprintk("Setting warm reset code and vector.\n"); \ if (clustered_apic_mode) { /* stash the current NMI vector, so we can put things back */ nmi_high = *((volatile unsigned short *) TRAMPOLINE_HIGH); nmi_low = *((volatile unsigned short *) TRAMPOLINE_LOW); } \ CMOS_WRITE(0xa, 0xf); local_flush_tlb(); Dprintk("1.\n"); *((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4; Dprintk("2.\n"); *((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf; Dprintk("3.\n"); \ /* * Be paranoid about clearing APIC errors. */ if (!clustered_apic_mode && APIC_INTEGRATED(apic_version[apicid])) { apic_read_around(APIC_SPIV); apic_write(APIC_ESR, 0); apic_read(APIC_ESR); } \ /* * Status is now clean */ boot_error = 0; \ /* * Starting actual IPI sequence... */ \ if (clustered_apic_mode) boot_error = wakeup_secondary_via_NMI(apicid); else boot_error = wakeup_secondary_via_INIT(apicid, start_eip); \ if (!boot_error) { /* * allow APs to start initializing. */ Dprintk("Before Callout %d.\n", cpu); set_bit(cpu, &cpu_callout_map); Dprintk("After Callout %d.\n", cpu); \ /* * Wait 5s total for a response */ for (timeout = 0; timeout < 50000; timeout++) { if (test_bit(cpu, &cpu_callin_map)) break; /* It has booted */ udelay(100); } \ if (test_bit(cpu, &cpu_callin_map)) { /* number CPUs logically, starting from 1 (BSP is 0) */ Dprintk("OK.\n"); printk("CPU%d: ", cpu); print_cpu_info(&cpu_data[cpu]); Dprintk("CPU has booted.\n"); } else { boot_error= 1; if (*((volatile unsigned char *)phys_to_virt(8192)) == 0xA5) /* trampoline started but...? */ printk("Stuck ??\n"); else /* trampoline code not run */ printk("Not responding.\n"); #if APIC_DEBUG if (!clustered_apic_mode) inquire_remote_apic(apicid); #endif } } if (boot_error) { /* Try to put things back the way they were before ... */ unmap_cpu_to_boot_apicid(cpu, apicid); clear_bit(cpu, &cpu_callout_map); /* was set here (do_boot_cpu()) */ clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ clear_bit(cpu, &cpu_online_map); /* was set in smp_callin() */ cpucount--; } \ /* mark "stuck" area as not stuck */ *((volatile unsigned long *)phys_to_virt(8192)) = 0; \ if(clustered_apic_mode) { printk("Restoring NMI vector\n"); *((volatile unsigned short *) TRAMPOLINE_HIGH) = nmi_high; *((volatile unsigned short *) TRAMPOLINE_LOW) = nmi_low; } } \ cycles_t cacheflush_time; unsigned long cache_decay_ticks; \ static void smp_tune_scheduling (void) { unsigned long cachesize; /* kB */ unsigned long bandwidth = 350; /* MB/s */ /* * Rough estimation for SMP scheduling, this is the number of * cycles it takes for a fully memory-limited process to flush * the SMP-local cache. * * (For a P5 this pretty much means we will choose another idle * CPU almost always at wakeup time (this is due to the small * L1 cache), on PIIs it's around 50-100 usecs, depending on * the cache size) */ \ if (!cpu_khz) { /* * this basically disables processor-affinity * scheduling on SMP without a TSC. */ cacheflush_time = 0; return; } else { cachesize = boot_cpu_data.x86_cache_size; if (cachesize == -1) { cachesize = 16; /* Pentiums, 2x8kB cache */ bandwidth = 100; } \ cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth; } \ cache_decay_ticks = (long)cacheflush_time/cpu_khz * HZ / 1000; \ printk("per-CPU timeslice cutoff: %ld.%02ld usecs.\n", (long)cacheflush_time/(cpu_khz/1000), ((long)cacheflush_time*100/(cpu_khz/1000)) % 100); printk("task migration cache decay timeout: %ld msecs.\n", (cache_decay_ticks + 1) * 1000 / HZ); } \ /* * Cycle through the processors sending APIC IPIs to boot each. */ \ extern int prof_multiplier[NR_CPUS]; extern int prof_old_multiplier[NR_CPUS]; extern int prof_counter[NR_CPUS]; \ static int boot_cpu_logical_apicid; /* Where the IO area was mapped on multiquad, always 0 otherwise */ void *xquad_portio = NULL; \ int cpu_sibling_map[NR_CPUS] __cacheline_aligned; \ void __init smp_boot_cpus(void) { int apicid, cpu, bit; \ if (clustered_apic_mode) { /* remap the 1st quad's 256k range for cross-quad I/O */ xquad_portio = ioremap (XQUAD_PORTIO_BASE, XQUAD_PORTIO_LEN); printk("Cross quad port I/O vaddr 0x%08lx, len %08lx\n", (u_long) xquad_portio, (u_long) XQUAD_PORTIO_LEN); } \ #ifdef CONFIG_MTRR /* Must be done before other processors booted */ mtrr_init_boot_cpu (); #endif /* * Initialize the logical to physical CPU number mapping * and the per-CPU profiling counter/multiplier */ \ for (cpu = 0; cpu < NR_CPUS; cpu++) { prof_counter[cpu] = 1; prof_old_multiplier[cpu] = 1; prof_multiplier[cpu] = 1; } \ init_cpu_to_apicid(); \ /* * Setup boot CPU information */ smp_store_cpu_info(0); /* Final full version of the data */ printk("CPU%d: ", 0); print_cpu_info(&cpu_data[0]); \ /* * We have the boot CPU online for sure. */ set_bit(0, &cpu_online_map); boot_cpu_logical_apicid = logical_smp_processor_id(); map_cpu_to_boot_apicid(0, boot_cpu_apicid); \ global_irq_holder = NO_PROC_ID; current_thread_info()->cpu = 0; smp_tune_scheduling(); \ /* * If we couldnt find an SMP configuration at boot time, * get out of here now! */ if (!smp_found_config) { printk(KERN_NOTICE "SMP motherboard not detected.\n"); #ifndef CONFIG_VISWS io_apic_irqs = 0; #endif cpu_online_map = phys_cpu_present_map = 1; smp_num_cpus = 1; if (APIC_init_uniprocessor()) printk(KERN_NOTICE "Local APIC not detected." " Using dummy APIC emulation.\n"); goto smp_done; } \ /* * Should not be necessary because the MP table should list the boot * CPU too, but we do it for the sake of robustness anyway. * Makes no sense to do this check in clustered apic mode, so skip it */ if (!clustered_apic_mode && !test_bit(boot_cpu_physical_apicid, &phys_cpu_present_map)) { printk("weird, boot CPU (#%d) not listed by the BIOS.\n", boot_cpu_physical_apicid); phys_cpu_present_map |= (1 << hard_smp_processor_id()); } \ /* * If we couldn't find a local APIC, then get out of here now! */ if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability)) { printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", boot_cpu_physical_apicid); printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); #ifndef CONFIG_VISWS io_apic_irqs = 0; #endif cpu_online_map = phys_cpu_present_map = 1; smp_num_cpus = 1; goto smp_done; } \ verify_local_APIC(); \ /* * If SMP should be disabled, then really disable it! */ if (!max_cpus) { smp_found_config = 0; printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); #ifndef CONFIG_VISWS io_apic_irqs = 0; #endif cpu_online_map = phys_cpu_present_map = 1; smp_num_cpus = 1; goto smp_done; } \ connect_bsp_APIC(); setup_local_APIC(); \ if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid) BUG(); \ /* * Scan the CPU present map and fire up the other CPUs via do_boot_cpu * * In clustered apic mode, phys_cpu_present_map is a constructed thus: * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the * clustered apic ID. */ Dprintk("CPU present map: %lx\n", phys_cpu_present_map); \ for (bit = 0; bit < NR_CPUS; bit++) { apicid = cpu_present_to_apicid(bit); /* * Don't even attempt to start the boot CPU! */ if (apicid == boot_cpu_apicid) continue; \ if (!(phys_cpu_present_map & (1 << bit))) continue; if ((max_cpus >= 0) && (max_cpus <= cpucount+1)) continue; \ do_boot_cpu(apicid); \ /* * Make sure we unmap all failed CPUs */ if ((boot_apicid_to_cpu(apicid) == -1) && (phys_cpu_present_map & (1 << bit))) printk("CPU #%d not responding - cannot use it.\n", apicid); } \ /* * Cleanup possible dangling ends... */ #ifndef CONFIG_VISWS { /* * Install writable page 0 entry to set BIOS data area. */ local_flush_tlb(); \ /* * Paranoid: Set warm reset code and vector here back * to default values. */ CMOS_WRITE(0, 0xf); \ *((volatile long *) phys_to_virt(0x467)) = 0; } #endif \ /* * Allow the user to impress friends. */ \ Dprintk("Before bogomips.\n"); if (!cpucount) { printk(KERN_ERR "Error: only one processor found.\n"); } else { unsigned long bogosum = 0; for (cpu = 0; cpu < NR_CPUS; cpu++) if (cpu_online_map & (1< 1) { for (cpu = 0; cpu < NR_CPUS; cpu++) cpu_sibling_map[cpu] = NO_PROC_ID; for (cpu = 0; cpu < smp_num_cpus; cpu++) { int i; for (i = 0; i < smp_num_cpus; i++) { if (i == cpu) continue; if (phys_proc_id[cpu] == phys_proc_id[i]) { cpu_sibling_map[cpu] = i; printk("cpu_sibling_map[%d] = %d\n", cpu, cpu_sibling_map[cpu]); break; } } if (cpu_sibling_map[cpu] == NO_PROC_ID) { smp_num_siblings = 1; printk(KERN_WARNING "WARNING: No sibling found for CPU %d.\n", cpu); } } } #ifndef CONFIG_VISWS /* * Here we can be sure that there is an IO-APIC in the system. Let's * go and set it up: */ if (!skip_ioapic_setup && nr_ioapics) setup_IO_APIC(); #endif \ /* * Set up all local APIC timers in the system: */ setup_APIC_clocks(); \ /* * Synchronize the TSC with the AP */ if (cpu_has_tsc && cpucount) synchronize_tsc_bp(); \ smp_done: zap_low_mappings(); } jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c.orig|20020310223326|52226 D 1.2 02/03/10 21:05:11-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Delete: arch/i386/kernel/smpboot.c.orig K 30827 O -rw-rw-r-- P BitKeeper/deleted/.del-smpboot.c.orig~4c5e910440eca7be ------------------------------------------------ == arch/i386/visws/Makefile == New file: arch/i386/visws/Makefile V 4 jejb@mulgrave.(none)|arch/i386/visws/Makefile|20020310223326|04124|86a8dbe92bf5299 D 1.0 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/visws/Makefile K 4124 P arch/i386/visws/Makefile R 86a8dbe92bf5299 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/visws/Makefile|20020310223326|04124|86a8dbe92bf5299 D 1.1 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +25 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 48283 O -rw-rw-r-- P arch/i386/visws/Makefile ------------------------------------------------ I0 25 # # Makefile for the linux kernel. # # Note! Dependencies are done automagically by 'make dep', which also # removes any old dependencies. DON'T put your own dependencies here # unless it's something special (ie not a .c file). # # Note 2! The CFLAGS definitions are now in the main makefile... \ .S.o: $(CC) $(AFLAGS) -traditional -c $< -o $*.o \ all: visws.o \ O_TARGET := visws.o EXTRA_CFLAGS += -I../kernel export-objs := \ obj-y := setup.o traps.o \ obj-$(CONFIG_PCI) += pci-visws.o obj-$(CONFIG_X86_VISWS_APIC) += visws_apic.o obj-$(CONFIG_X86_LOCAL_APIC) += mpparse.o \ include $(TOPDIR)/Rules.make == arch/i386/visws/do_timer.h == New file: arch/i386/visws/do_timer.h V 4 jejb@mulgrave.(none)|arch/i386/visws/do_timer.h|20020310223326|07933|af96030dfb8161cd D 1.0 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/visws/do_timer.h K 7933 P arch/i386/visws/do_timer.h R af96030dfb8161cd X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/visws/do_timer.h|20020310223326|07933|af96030dfb8161cd D 1.1 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +24 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 55354 O -rw-rw-r-- P arch/i386/visws/do_timer.h ------------------------------------------------ I0 24 /* defines for inline arch setup functions */ \ #include #include \ static inline void do_timer_interrupt_hook(struct pt_regs *regs) { /* Clear the interrupt */ co_cpu_write(CO_CPU_STAT,co_cpu_read(CO_CPU_STAT) & ~CO_STAT_TIMEINTR); \ do_timer(regs); /* * In the SMP case we use the local APIC timer interrupt to do the * profiling, except when we simulate SMP mode on a uniprocessor * system, in that case we have to call the local interrupt handler. */ #ifndef CONFIG_X86_LOCAL_APIC if (!user_mode(regs)) x86_do_profile(regs->eip); #else if (!using_apic_timer) smp_local_timer_interrupt(regs); #endif } jejb@mulgrave.(none)|arch/i386/visws/do_timer.h|20020310223327|55354 D 1.2 02/03/11 17:08:44-05:00 jejb@mulgrave.(none) +26 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add do_timer_overflow() K 33373 O -rw-rw-r-- P arch/i386/visws/do_timer.h ------------------------------------------------ I24 26 \ static inline int do_timer_overflow(int count) { int i; \ spin_lock(&i8259A_lock); /* * This is tricky when I/O APICs are used; * see do_timer_interrupt(). */ i = inb(0x20); spin_unlock(&i8259A_lock); /* assumption about timer being IRQ0 */ if (i & 0x01) { /* * We cannot detect lost timer interrupts ... * well, that's why we call them lost, don't we? :) * [hmm, on the Pentium and Alpha we can ... sort of] */ count -= LATCH; } else { printk("do_slow_gettimeoffset(): hardware timer problem?\n"); } return count; } == arch/i386/visws/mpparse.c == New file: arch/i386/visws/mpparse.c V 4 jejb@mulgrave.(none)|arch/i386/visws/mpparse.c|20020310223326|11757|d6f57800c1cb0c1d D 1.0 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/visws/mpparse.c K 11757 P arch/i386/visws/mpparse.c R d6f57800c1cb0c1d X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/visws/mpparse.c|20020310223326|11757|d6f57800c1cb0c1d D 1.1 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +67 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 6758 O -rw-rw-r-- P arch/i386/visws/mpparse.c ------------------------------------------------ I0 67 #include #include #include #include #include #include #include #include #include \ #include #include #include #include \ /* Have we found an MP table */ int smp_found_config; \ /* * Various Linux-internal data structures created from the * MP-table. */ int apic_version [MAX_APICS]; int mp_bus_id_to_type [MAX_MP_BUSSES]; int mp_bus_id_to_node [MAX_MP_BUSSES]; int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; int mp_current_pci_id; \ /* I/O APIC entries */ struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; \ /* # of MP IRQ source entries */ struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; \ /* MP IRQ source entries */ int mp_irq_entries; \ int nr_ioapics; \ int pic_mode; unsigned long mp_lapic_addr; \ /* Processor that is doing the boot up */ unsigned int boot_cpu_physical_apicid = -1U; unsigned int boot_cpu_logical_apicid = -1U; /* Internal processor count */ static unsigned int num_processors; \ /* Bitmask of physically existing CPUs */ unsigned long phys_cpu_present_map; \ /* * The Visual Workstation is Intel MP compliant in the hardware * sense, but it doesnt have a BIOS(-configuration table). * No problem for Linux. */ void __init find_smp_config(void) { smp_found_config = 1; \ phys_cpu_present_map |= 2; /* or in id 1 */ apic_version[1] |= 0x10; /* integrated APIC */ apic_version[0] |= 0x10; \ mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; } \ == arch/i386/visws/setup_arch.h == New file: arch/i386/visws/setup_arch.h V 4 jejb@mulgrave.(none)|arch/i386/visws/setup_arch.h|20020311052758|09863|129d6f33bc082b26 D 1.0 02/03/11 00:27:58-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/visws/setup_arch.h K 9863 P arch/i386/visws/setup_arch.h R 129d6f33bc082b26 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/visws/setup_arch.h|20020311052758|09863|129d6f33bc082b26 D 1.1 02/03/11 00:27:58-05:00 jejb@mulgrave.(none) +34 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 57780 O -rw-rw-r-- P arch/i386/visws/setup_arch.h ------------------------------------------------ I0 34 #ifdef SETUP_POST static inline char * __init machine_specific_memory_setup(void) { char *who; \ \ who = "BIOS-e820"; \ /* * Try to copy the BIOS-supplied E820-map. * * Otherwise fake a memory map; one section from 0k->640k, * the next section from 1mb->appropriate_mem_k */ sanitize_e820_map(E820_MAP, &E820_MAP_NR); if (copy_e820_map(E820_MAP, E820_MAP_NR) < 0) { unsigned long mem_size; \ /* compare results from other methods and take the greater */ if (ALT_MEM_K < EXT_MEM_K) { mem_size = EXT_MEM_K; who = "BIOS-88"; } else { mem_size = ALT_MEM_K; who = "BIOS-e801"; } \ e820.nr_map = 0; add_memory_region(0, LOWMEMSIZE(), E820_RAM); add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM); } return who; } #endif jejb@mulgrave.(none)|arch/i386/visws/setup_arch.h|20020311052759|57780 D 1.2 02/03/11 00:59:30-05:00 jejb@mulgrave.(none) +3 -1 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c add ARCH_SETUP hook K 59838 O -rw-rw-r-- P arch/i386/visws/setup_arch.h ------------------------------------------------ D1 1 I1 3 #ifndef SETUP_POST #define ARCH_SETUP #else == arch/i386/visws/traps.c == New file: arch/i386/visws/traps.c V 4 jejb@mulgrave.(none)|arch/i386/visws/traps.c|20020310223326|15572|91a4f00b62c56fa9 D 1.0 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/arch/i386/visws/traps.c K 15572 P arch/i386/visws/traps.c R 91a4f00b62c56fa9 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/visws/traps.c|20020310223326|15572|91a4f00b62c56fa9 D 1.1 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +134 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 24932 O -rw-rw-r-- P arch/i386/visws/traps.c ------------------------------------------------ I0 134 /* VISWS traps */ \ #include #include #include #include #include #include #include #include #include #include #include #include #include #include \ #include #include #include #include #include #include #include \ #include #include #include \ #ifdef CONFIG_X86_VISWS_APIC #include #include #include #endif \ #ifdef CONFIG_X86_VISWS_APIC \ /* * On Rev 005 motherboards legacy device interrupt lines are wired directly * to Lithium from the 307. But the PROM leaves the interrupt type of each * 307 logical device set appropriate for the 8259. Later we'll actually use * the 8259, but for now we have to flip the interrupt types to * level triggered, active lo as required by Lithium. */ \ #define REG 0x2e /* The register to read/write */ #define DEV 0x07 /* Register: Logical device select */ #define VAL 0x2f /* The value to read/write */ \ static void superio_outb(int dev, int reg, int val) { outb(DEV, REG); outb(dev, VAL); outb(reg, REG); outb(val, VAL); } \ static int __attribute__ ((unused)) superio_inb(int dev, int reg) { outb(DEV, REG); outb(dev, VAL); outb(reg, REG); return inb(VAL); } \ #define FLOP 3 /* floppy logical device */ #define PPORT 4 /* parallel logical device */ #define UART5 5 /* uart2 logical device (not wired up) */ #define UART6 6 /* uart1 logical device (THIS is the serial port!) */ #define IDEST 0x70 /* int. destination (which 307 IRQ line) reg. */ #define ITYPE 0x71 /* interrupt type register */ \ /* interrupt type bits */ #define LEVEL 0x01 /* bit 0, 0 == edge triggered */ #define ACTHI 0x02 /* bit 1, 0 == active lo */ \ static __init void superio_init(void) { if (visws_board_type == VISWS_320 && visws_board_rev == 5) { superio_outb(UART6, IDEST, 0); /* 0 means no intr propagated */ printk("SGI 320 rev 5: disabling 307 uart1 interrupt\n"); } } \ static __init void lithium_init(void) { set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS); printk("Lithium PCI Bridge A, Bus Number: %d\n", li_pcia_read16(LI_PCI_BUSNUM) & 0xff); set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS); printk("Lithium PCI Bridge B (PIIX4), Bus Number: %d\n", li_pcib_read16(LI_PCI_BUSNUM) & 0xff); \ /* XXX blindly enables all interrupts */ li_pcia_write16(LI_PCI_INTEN, 0xffff); li_pcib_write16(LI_PCI_INTEN, 0xffff); } \ static __init void cobalt_init(void) { /* * On normal SMP PC this is used only with SMP, but we have to * use it and set it up here to start the Cobalt clock */ set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE); printk("Local APIC ID %lx\n", apic_read(APIC_ID)); printk("Local APIC Version %lx\n", apic_read(APIC_LVR)); \ set_fixmap(FIX_CO_CPU, CO_CPU_PHYS); printk("Cobalt Revision %lx\n", co_cpu_read(CO_CPU_REV)); \ set_fixmap(FIX_CO_APIC, CO_APIC_PHYS); printk("Cobalt APIC ID %lx\n", co_apic_read(CO_APIC_ID)); \ /* Enable Cobalt APIC being careful to NOT change the ID! */ co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID)|CO_APIC_ENABLE); \ printk("Cobalt APIC enabled: ID reg %lx\n", co_apic_read(CO_APIC_ID)); } #endif \ void __init trap_init_hook() { #ifdef CONFIG_X86_VISWS_APIC superio_init(); lithium_init(); cobalt_init(); #endif } == include/asm-i386/arch_hooks.h == New file: include/asm-i386/arch_hooks.h V 4 jejb@mulgrave.(none)|include/asm-i386/arch_hooks.h|20020310223326|19449|4214d3776d55c82 D 1.0 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c BitKeeper file /home/jejb/BK/abstract-i386-2.5/include/asm-i386/arch_hooks.h K 19449 P include/asm-i386/arch_hooks.h R 4214d3776d55c82 X 0x821 ------------------------------------------------ jejb@mulgrave.(none)|include/asm-i386/arch_hooks.h|20020310223326|19449|4214d3776d55c82 D 1.1 02/03/10 17:33:26-05:00 jejb@mulgrave.(none) +24 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C F 1 K 55968 O -rw-rw-r-- P include/asm-i386/arch_hooks.h ------------------------------------------------ I0 24 #ifndef _ASM_ARCH_HOOKS_H #define _ASM_ARCH_HOOKS_H \ /* * linux/include/asm/arch_hooks.h * * define the architecture specific hooks */ \ /* these aren't arch hooks, they are generic routines * that can be used by the hooks */ extern void init_ISA_irqs(void); extern void apic_intr_init(void); extern void smp_intr_init(void); extern void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs); \ /* these are the defined hooks */ extern void intr_init_hook(void); extern void pre_intr_init_hook(void); extern void pre_setup_arch_hook(void); extern void trap_init_hook(void); extern void time_init_hook(void); \ #endif jejb@mulgrave.(none)|include/asm-i386/arch_hooks.h|20020310223327|55968 D 1.2 02/03/10 22:00:12-05:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c add mca nmi hook K 58964 O -rw-rw-r-- P include/asm-i386/arch_hooks.h ------------------------------------------------ I22 1 extern void mca_nmi_hook(void); == arch/i386/visws/setup.c == patch@athlon.transmeta.com|arch/i386/kernel/setup-visws.c|20020205235942|42465|e5b21413e86afce8 patch@athlon.transmeta.com|arch/i386/kernel/setup-visws.c|20020205235943|41936 D 1.2 02/03/10 10:23:25-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Rename: arch/i386/kernel/setup-visws.c -> arch/i386/visws/setup.c K 28937 O -rw-rw-r-- P arch/i386/visws/setup.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/visws/setup.c|20020310152325|28937 D 1.3 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +49 -5 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Make setup more generic K 60599 O -rw-rw-r-- P arch/i386/visws/setup.c ------------------------------------------------ I5 10 #include #include #include #include \ #include #include #include #include \ D121 5 I125 39 printk(KERN_INFO "Silicon Graphics %s (rev %d)\n", visws_board_type == VISWS_320 ? "320" : (visws_board_type == VISWS_540 ? "540" : "unknown"), visws_board_rev); } \ void __init pre_intr_init_hook(void) { init_VISWS_APIC_irqs(); } \ void __init intr_init_hook(void) { #ifdef CONFIG_X86_LOCAL_APIC apic_intr_init(); #endif } \ void __init pre_setup_arch_hook() { visws_get_board_type_and_rev(); } static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL}; \ void __init time_init_hook(void) { printk("Starting Cobalt Timer system clock\n"); \ /* Set the countdown value */ co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ); \ /* Start the timer */ co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN); \ /* Enable (unmask) the timer interrupt */ co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK); \ /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */ setup_irq(CO_IRQ_TIMER, &irq0); == arch/i386/Makefile == torvalds@athlon.transmeta.com|arch/i386/Makefile|20020205174020|18710|1b8aa1f0c40a1dbf patch@athlon.transmeta.com|arch/i386/Makefile|20020205181134|59073 D 1.4 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +13 -2 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add MACHINE variable (as done in arch/arm) K 5334 O -rw-rw-r-- P arch/i386/Makefile ------------------------------------------------ I88 6 ifdef CONFIG_VISWS MACHINE := visws else MACHINE := generic endif \ D91 1 I91 5 SUBDIRS += arch/i386/kernel arch/i386/mm arch/i386/lib \ arch/i386/$(MACHINE) \ CORE_FILES := arch/i386/kernel/kernel.o arch/i386/mm/mm.o \ arch/i386/$(MACHINE)/$(MACHINE).o $(CORE_FILES) D93 1 I94 2 \ CFLAGS += -I$(TOPDIR)/arch/i386/$(MACHINE) == arch/i386/config.in == torvalds@athlon.transmeta.com|arch/i386/config.in|20020205174020|19554|3014fe999baf20a0 mingo@elte.hu|arch/i386/config.in|20020219152738|13936 D 1.28 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +8 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add extra irqs definition - used to define extra IRQ gates (used by c both SMP systems and local APIC UP systems) c Add CONIFG_X86_SMP as local gate for including the kernel/smp.o K 24982 O -rw-rw-r-- P arch/i386/config.in ------------------------------------------------ I419 4 if [ "$CONFIG_X86_LOCAL_APIC" = "y" ]; then define_bool CONFIG_X86_EXTRA_IRQS y fi \ N422 4 \ if [ "$CONFIG_SMP" = "y" ]; then define_bool CONFIG_X86_SMP y fi jejb@mulgrave.(none)|arch/i386/config.in|20020310223325|24982 D 1.29 02/03/10 19:16:39-05:00 jejb@mulgrave.(none) +1 -1 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add missing \n K 24992 O -rw-rw-r-- P arch/i386/config.in ------------------------------------------------ D430 1 I430 1 fi jejb@mulgrave.(none)|arch/i386/config.in|20020311001639|24992 D 1.30 02/03/11 13:31:47-05:00 jejb@mulgrave.(none) +3 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add new defines for c c - hyperthreading CONFIG_X86_HT c - reboot through bios CONFIG_X86_BIOS_REBOOT K 30348 O -rw-rw-r-- P arch/i386/config.in ------------------------------------------------ I429 1 define_bool CONFIG_X86_HT y I430 2 \ define_bool CONFIG_X86_BIOS_REBOOT y jejb@mulgrave.(none)|arch/i386/config.in|20020311183147|30348 D 1.31 02/03/11 17:08:44-05:00 jejb@mulgrave.(none) +4 -3 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c - add find smp config define c - alter indentation to conform to correct norm K 34025 O -rw-rw-r-- P arch/i386/config.in ------------------------------------------------ D421 1 I421 2 define_bool CONFIG_X86_EXTRA_IRQS y define_bool CONFIG_X86_FIND_SMP_CONFIG y D429 2 I430 2 define_bool CONFIG_X86_SMP y define_bool CONFIG_X86_HT y jejb@mulgrave.(none)|arch/i386/config.in|20020311220844|34025 D 1.32 02/03/19 13:41:39-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i bgerst@didntduck.org|arch/i386/config.in|20020315231547|27996 i agrover@groveronline.com|arch/i386/config.in|20020315232830|18077 i dalecki@evision-ventures.com|arch/i386/config.in|20020318185719|14811 K 34900 M dalecki@evision-ventures.com|arch/i386/config.in|20020318185719|14811 O -rw-rw-r-- P arch/i386/config.in ------------------------------------------------ == arch/i386/kernel/Makefile == torvalds@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205174021|44365|51bedff053cda0cd patch@athlon.transmeta.com|arch/i386/kernel/Makefile|20020205235942|35096 D 1.4.1.1 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +3 -15 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c - Remove VISWS stuff c - gate smp.o etc. on CONFIG_X86_SMP K 19362 O -rw-rw-r-- P arch/i386/kernel/Makefile ------------------------------------------------ D24 9 I32 1 obj-$(CONFIG_PCI) += pci-i386.o D39 2 I40 2 obj-$(CONFIG_X86_SMP) += smp.o smpboot.o trampoline.o obj-$(CONFIG_X86_LOCAL_APIC) += apic.o nmi.o D42 4 jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020310223325|19362 D 1.4.1.2 02/03/11 13:31:47-05:00 jejb@mulgrave.(none) +1 -1 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add new bios reboot functions file (split from process.c) K 22473 O -rw-rw-r-- P arch/i386/kernel/Makefile ------------------------------------------------ D23 1 I23 1 obj-$(CONFIG_X86_BIOS_REBOOT) += reboot.o torvalds@penguin.transmeta.com|arch/i386/kernel/Makefile|20020308003450|35716 D 1.6 02/03/11 18:12:57-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020310223325|19362 i jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311183147|22473 K 23093 M jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311183147|22473 O -rw-rw-r-- P arch/i386/kernel/Makefile ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/kernel/Makefile|20020311231257|23093 D 1.7 02/03/19 13:47:37-08:00 jejb@mulgrave.(none) +0 -2 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Merge by hand i agrover@groveronline.com|arch/i386/kernel/Makefile|20020315232830|39863 K 21971 M agrover@groveronline.com|arch/i386/kernel/Makefile|20020315232830|39863 O -rw-rw-r-- P arch/i386/kernel/Makefile ------------------------------------------------ D31 2 == arch/i386/kernel/apic.c == torvalds@athlon.transmeta.com|arch/i386/kernel/apic.c|20020205174021|04808|71c663f64b1844f0 davej@suse.de|arch/i386/kernel/apic.c|20020226193546|31627 D 1.13 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +26 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Moved apic interrupt gates in here K 42261 O -rw-rw-r-- P arch/i386/kernel/apic.c ------------------------------------------------ I31 26 #include #include \ /* * every pentium local APIC has two 'local interrupts', with a * soft-definable vector attached to both interrupts, one of * which is a timer interrupt, the other one is error counter * overflow. Linux uses the local APIC timer interrupt to get * a much simpler SMP time architecture: */ BUILD_SMP_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR) BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR) BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR) \ void __init apic_intr_init(void) { #ifdef CONFIG_SMP smp_intr_init(); #endif /* self generated IPI for local APIC timer */ set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); \ /* IPI vectors for APIC spurious and error interrupts */ set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); } == arch/i386/kernel/i8259.c == torvalds@athlon.transmeta.com|arch/i386/kernel/i8259.c|20020205174021|59798|fc99768517501f14 mingo@elte.hu|arch/i386/kernel/i8259.c|20020221161007|11930 D 1.8 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +6 -73 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c - changed extra interrupt build to be gated by CONFIG_X86_EXTRA_IRQS c define c - removed local apic interrupt gate definition to apic.c c - removed smp io-apic interrupt gate definition to smpboot.c c - added smp_intr_init() hook (hooks to smpboot.c) K 42500 O -rw-rw-r-- P arch/i386/kernel/i8259.c ------------------------------------------------ I23 1 #include D55 1 I55 1 #ifdef CONFIG_X86_EXTRA_IRQS D75 25 D112 1 I112 1 #ifdef CONFIG_X86_EXTRA_IRQS D406 9 D447 5 I451 2 pre_intr_init_hook(); \ D463 28 I490 1 intr_init_hook(); D499 4 == arch/i386/kernel/mca.c == torvalds@athlon.transmeta.com|arch/i386/kernel/mca.c|20020205174021|58816|d911d404e1d0ea6 patch@athlon.transmeta.com|arch/i386/kernel/mca.c|20020206001644|26853 D 1.5 02/03/10 22:00:12-05:00 jejb@mulgrave.(none) +1 -6 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c hook out nmi K 10518 O -rw-rw-r-- P arch/i386/kernel/mca.c ------------------------------------------------ D374 6 I379 1 mca_nmi_hook(); jejb@mulgrave.(none)|arch/i386/kernel/mca.c|20020311030012|10518 D 1.6 02/03/11 17:08:44-05:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c add missed include for arch hooks. K 13032 O -rw-rw-r-- P arch/i386/kernel/mca.c ------------------------------------------------ I54 1 #include == arch/i386/generic/mpparse.c == torvalds@athlon.transmeta.com|arch/i386/kernel/mpparse.c|20020205174021|05759|a518369612979315 patch@athlon.transmeta.com|arch/i386/kernel/mpparse.c|20020205203239|42538 D 1.6.1.1 02/03/10 15:21:31-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Rename: arch/i386/kernel/mpparse.c -> arch/i386/generic/mpparse.c K 26674 O -rw-rw-r-- P arch/i386/generic/mpparse.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020310202131|26674 D 1.6.1.2 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +2 -36 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Make MP parsing generic and remove VISWS stuff K 54934 O -rw-rw-r-- P arch/i386/generic/mpparse.c ------------------------------------------------ D70 1 I70 1 \ D773 1 I773 1 void __init find_smp_config (void) D809 34 Martin.Bligh@us.ibm.com|arch/i386/kernel/mpparse.c|20020308005401|61398 D 1.8 02/03/11 18:12:57-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Merge rename: arch/i386/kernel/mpparse.c -> arch/i386/generic/mpparse.c K 38219 O -rw-rw-r-- P arch/i386/generic/mpparse.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020311231257|38219 D 1.9 02/03/11 18:12:57-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged F 1 i jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020310202131|26674 i jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020310223325|54934 K 8258 M jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020310223325|54934 O -rw-rw-r-- P arch/i386/generic/mpparse.c ------------------------------------------------ agrover@groveronline.com|arch/i386/kernel/mpparse.c|20020315232857|40516 D 1.7.1.2 02/03/19 13:41:38-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Merge rename: arch/i386/kernel/mpparse.c -> arch/i386/generic/mpparse.c K 18973 O -rw-rw-r-- P arch/i386/generic/mpparse.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020311231258|08258 D 1.10 02/03/19 13:41:39-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i agrover@groveronline.com|arch/i386/kernel/mpparse.c|20020315232857|40516 i jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020319214138|18973 K 52912 M jejb@mulgrave.(none)|arch/i386/generic/mpparse.c|20020319214138|18973 O -rw-rw-r-- P arch/i386/generic/mpparse.c ------------------------------------------------ == arch/i386/generic/pci-irq.c == torvalds@athlon.transmeta.com|arch/i386/kernel/pci-irq.c|20020205174021|08531|4fd93b99df3a709f patch@athlon.transmeta.com|arch/i386/kernel/pci-irq.c|20020205203008|12850 D 1.12 02/03/10 10:23:45-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Rename: arch/i386/kernel/pci-irq.c -> arch/i386/generic/pci-irq.c K 13517 O -rw-rw-r-- P arch/i386/generic/pci-irq.c ------------------------------------------------ agrover@groveronline.com|arch/i386/kernel/pci-irq.c|20020315232857|64973 D 1.11.1.3 02/03/19 13:41:38-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Merge rename: arch/i386/kernel/pci-irq.c -> arch/i386/generic/pci-irq.c K 23114 O -rw-rw-r-- P arch/i386/generic/pci-irq.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/pci-irq.c|20020310152345|13517 D 1.13 02/03/19 13:41:39-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i john@deater.net|arch/i386/kernel/pci-irq.c|20020312205311|39305 i agrover@groveronline.com|arch/i386/kernel/pci-irq.c|20020315232857|64973 i jejb@mulgrave.(none)|arch/i386/generic/pci-irq.c|20020319214138|23114 K 64973 M jejb@mulgrave.(none)|arch/i386/generic/pci-irq.c|20020319214138|23114 O -rw-rw-r-- P arch/i386/generic/pci-irq.c ------------------------------------------------ == arch/i386/generic/pci-pc.c == torvalds@athlon.transmeta.com|arch/i386/kernel/pci-pc.c|20020205174021|63770|524c79ffe499fd6b patch@athlon.transmeta.com|arch/i386/kernel/pci-pc.c|20020205235931|30204 D 1.18.1.1 02/03/10 10:23:45-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Rename: arch/i386/kernel/pci-pc.c -> arch/i386/generic/pci-pc.c K 9047 O -rw-rw-r-- P arch/i386/generic/pci-pc.c ------------------------------------------------ Martin.Bligh@us.ibm.com|arch/i386/kernel/pci-pc.c|20020308005401|01926 D 1.20 02/03/11 18:12:57-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Merge rename: arch/i386/kernel/pci-pc.c -> arch/i386/generic/pci-pc.c K 43284 O -rw-rw-r-- P arch/i386/generic/pci-pc.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020311231257|43284 D 1.21 02/03/11 18:12:57-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged F 1 i jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020310152345|09047 K 1926 M jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020310152345|09047 O -rw-rw-r-- P arch/i386/generic/pci-pc.c ------------------------------------------------ agrover@groveronline.com|arch/i386/kernel/pci-pc.c|20020315232857|50253 D 1.19.1.3 02/03/19 13:41:38-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 c Merge rename: arch/i386/kernel/pci-pc.c -> arch/i386/generic/pci-pc.c K 28554 O -rw-rw-r-- P arch/i386/generic/pci-pc.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020311231258|01926 D 1.22 02/03/19 13:41:40-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i john@deater.net|arch/i386/kernel/pci-pc.c|20020312205311|09254 i agrover@groveronline.com|arch/i386/kernel/pci-pc.c|20020315232857|50253 i jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020319214138|28554 K 50253 M jejb@mulgrave.(none)|arch/i386/generic/pci-pc.c|20020319214138|28554 O -rw-rw-r-- P arch/i386/generic/pci-pc.c ------------------------------------------------ == arch/i386/visws/pci-visws.c == torvalds@athlon.transmeta.com|arch/i386/kernel/pci-visws.c|20020205174021|03903|8effe20055c2f553 patch@athlon.transmeta.com|arch/i386/kernel/pci-visws.c|20020205203008|65391 D 1.3 02/03/10 10:23:05-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Rename: arch/i386/kernel/pci-visws.c -> arch/i386/visws/pci-visws.c K 27108 O -rw-rw-r-- P arch/i386/visws/pci-visws.c ------------------------------------------------ == arch/i386/kernel/process.c == torvalds@athlon.transmeta.com|arch/i386/kernel/process.c|20020205174021|49308|2ad581b9d9a74cc6 mingo@elte.hu|arch/i386/kernel/process.c|20020219152738|01482 D 1.20 02/03/11 13:31:47-05:00 jejb@mulgrave.(none) +0 -286 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Split reboot funtions out into reboot.c K 63225 O -rw-rw-r-- P arch/i386/kernel/process.c ------------------------------------------------ D70 5 D162 281 == arch/i386/kernel/setup.c == torvalds@athlon.transmeta.com|arch/i386/kernel/setup.c|20020205174021|47310|a1041e741f1cc275 davej@suse.de|arch/i386/kernel/setup.c|20020226193546|01549 D 1.42 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +2 -3 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Add arch hook K 1011 O -rw-rw-r-- P arch/i386/kernel/setup.c ------------------------------------------------ I115 1 #include D677 3 I679 1 pre_setup_arch_hook(); jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020310223325|01011 D 1.43 02/03/11 00:27:58-05:00 jejb@mulgrave.(none) +9 -24 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Split into arch specific setup piece for memory initialisation K 36713 O -rw-rw-r-- P arch/i386/kernel/setup.c ------------------------------------------------ I116 3 #include "setup_arch.h" \ static inline char * __init machine_specific_memory_setup(void); D561 1 I561 1 char *who = machine_specific_memory_setup(); D563 23 I682 1 #ifdef CONFIG_APM I683 1 #endif I2910 3 \ #define SETUP_POST #include "setup_arch.h" jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311052758|36713 D 1.44 02/03/11 00:59:30-05:00 jejb@mulgrave.(none) +1 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c add ARCH_SETUP hook K 37514 O -rw-rw-r-- P arch/i386/kernel/setup.c ------------------------------------------------ I678 1 ARCH_SETUP jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311055930|37514 D 1.45 02/03/11 13:31:47-05:00 jejb@mulgrave.(none) +1 -1 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c A K 37723 O -rw-rw-r-- P arch/i386/kernel/setup.c ------------------------------------------------ D2118 1 I2118 1 #ifdef CONFIG_X86_HT jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311183147|37723 D 1.46 02/03/11 17:08:44-05:00 jejb@mulgrave.(none) +1 -1 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c make find_smp_config() gated by define of similar name K 38137 O -rw-rw-r-- P arch/i386/kernel/setup.c ------------------------------------------------ D855 1 I855 1 #ifdef CONFIG_X86_FIND_SMP_CONFIG jejb@mulgrave.(none)|arch/i386/kernel/setup.c|20020311220844|38137 D 1.47 02/03/19 13:41:40-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i bgerst@didntduck.org|arch/i386/kernel/setup.c|20020315231547|00029 i agrover@groveronline.com|arch/i386/kernel/setup.c|20020315232857|21954 K 58542 M agrover@groveronline.com|arch/i386/kernel/setup.c|20020315232857|21954 O -rw-rw-r-- P arch/i386/kernel/setup.c ------------------------------------------------ == arch/i386/kernel/smpboot.c == torvalds@athlon.transmeta.com|arch/i386/kernel/smpboot.c|20020205174021|01101|c1d3f8ed92734a56 rusty@rustcorp.com.au|arch/i386/kernel/smpboot.c|20020302213249|52226 D 1.16.1.1 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +34 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c - Added io-apic interrupt gate definition c - added smp_intr_init() hook for initialising gates in io-apic K 5933 O -rw-rw-r-- P arch/i386/kernel/smpboot.c ------------------------------------------------ I50 2 #include #include I1250 32 } \ extern void (*interrupt[NR_IRQS])(void); \ /* * The following vectors are part of the Linux architecture, there * is no hardware IRQ pin equivalent for them, they are triggered * through the ICC by us (IPIs) */ BUILD_SMP_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR) BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR) BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR) \ void __init smp_intr_init() { /* * IRQ0 must be given a fixed assignment and initialized, * because it's used before the IO-APIC is set up. */ set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); \ /* * The reschedule interrupt is a CPU-to-CPU reschedule-helper * IPI, driven by wakeup. */ set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); \ /* IPI for invalidation */ set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); \ /* IPI for generic function call */ set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); Martin.Bligh@us.ibm.com|arch/i386/kernel/smpboot.c|20020308005401|56422 D 1.18 02/03/11 18:12:57-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020310223325|05933 K 10129 M jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020310223325|05933 O -rw-rw-r-- P arch/i386/kernel/smpboot.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/kernel/smpboot.c|20020311231257|10129 D 1.19 02/03/19 13:41:40-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i torvalds@home.transmeta.com|arch/i386/kernel/smpboot.c|20020315223053|56495 K 10202 M torvalds@home.transmeta.com|arch/i386/kernel/smpboot.c|20020315223053|56495 O -rw-rw-r-- P arch/i386/kernel/smpboot.c ------------------------------------------------ == arch/i386/kernel/time.c == torvalds@athlon.transmeta.com|arch/i386/kernel/time.c|20020205174021|55064|21a3bd924f02077 vojtech@suse.cz|arch/i386/kernel/time.c|20020226212601|00890 D 1.6.1.1 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +9 -39 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c - make TSC code be surrounded by CONFIG_X86_TSC K 53563 O -rw-rw-r-- P arch/i386/kernel/time.c ------------------------------------------------ D58 2 I59 2 #include #include "do_timer.h" D412 17 I428 1 do_timer_interrupt_hook(regs); D469 1 I469 1 void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) D559 2 I572 1 #ifdef CONFIG_X86_TSC I636 1 #endif /* CONFIG_X86_TSC */ I658 1 #ifdef CONFIG_X86_TSC I698 1 #endif /* CONFIG_X86_TSC */ D700 17 I716 1 time_init_hook(); jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020310223325|53563 D 1.6.1.2 02/03/11 17:08:44-05:00 jejb@mulgrave.(none) +4 -39 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c alter structure to have timer overflow done by inline function c from do_timer.h K 54491 O -rw-rw-r-- P arch/i386/kernel/time.c ------------------------------------------------ I58 3 \ extern spinlock_t i8259A_lock; \ D120 2 D202 3 D209 34 I242 1 count = do_timer_overflow(count); torvalds@penguin.transmeta.com|arch/i386/kernel/time.c|20020308003450|03232 D 1.8 02/03/11 18:12:58-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020310223325|53563 i jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311220844|54491 K 56833 M jejb@mulgrave.(none)|arch/i386/kernel/time.c|20020311220844|54491 O -rw-rw-r-- P arch/i386/kernel/time.c ------------------------------------------------ == arch/i386/kernel/traps.c == torvalds@athlon.transmeta.com|arch/i386/kernel/traps.c|20020205174021|43275|f01e9a814d3e2866 davej@suse.de|arch/i386/kernel/traps.c|20020226193546|59128 D 1.18.1.1 02/03/10 17:33:25-05:00 jejb@mulgrave.(none) +2 -101 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c - add arch hook c - remove visws stuff K 31734 O -rw-rw-r-- P arch/i386/kernel/traps.c ------------------------------------------------ D43 6 I48 1 #include D880 90 D1016 5 I1020 1 trap_init_hook(); torvalds@penguin.transmeta.com|arch/i386/kernel/traps.c|20020308003603|62155 D 1.20 02/03/11 18:12:58-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020310223325|31734 K 34761 M jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020310223325|31734 O -rw-rw-r-- P arch/i386/kernel/traps.c ------------------------------------------------ jejb@mulgrave.(none)|arch/i386/kernel/traps.c|20020311231258|34761 D 1.21 02/03/19 13:41:40-08:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Auto merged i bgerst@didntduck.org|arch/i386/kernel/traps.c|20020315231547|28801 K 1407 M bgerst@didntduck.org|arch/i386/kernel/traps.c|20020315231547|28801 O -rw-rw-r-- P arch/i386/kernel/traps.c ------------------------------------------------ == arch/i386/visws/visws_apic.c == torvalds@athlon.transmeta.com|arch/i386/kernel/visws_apic.c|20020205174021|64746|1b0f0254adaacb49 patch@athlon.transmeta.com|arch/i386/kernel/visws_apic.c|20020205175704|58423 D 1.3 02/03/10 10:22:50-05:00 jejb@mulgrave.(none) +0 -0 B torvalds@athlon.transmeta.com|ChangeSet|20020205173056|16047|c1d11a41ed024864 C c Rename: arch/i386/kernel/visws_apic.c -> arch/i386/visws/visws_apic.c K 46020 O -rw-rw-r-- P arch/i386/visws/visws_apic.c ------------------------------------------------ # Patch checksum=a78a8c34